Global Routing

ENTITY test is port a: in bit; end ENTITY test; System Specification Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis Architectural Design ENTITY test is port a: in bit; end ENTITY test; Functional Design and Logic Design Circuit Design Physical Design Physical Verification and Signoff DRC LVS ERC Fabrication Packaging and Testing Chip

Problem Definition Input: Output: Objectives: Constraints: Netlist Locations of blocks and locations of pins Technology information Timing budget for, typically, critical nets Output: Geometric layouts of all nets Objectives: Minimize the total wire length # of vias or just completing all connections without increasing the chip area Constraints: Design rules Routing resource capacities Timing budget of each net

Types of Routing Problems Fixed-die routing: Chip outline and routing resources are fixed. Variable-die routing: New routing tracks can be added as needed.

General Routing Problem Two phases: Global Routing Detailed Routing

Introduction Routing Multi-Stage Routing of Signal Nets Global Routing Detailed Routing Timing-Driven Routing Large Single- Net Routing Geometric Techniques Coarse-grain assignment of routes to routing regions Fine-grain assignment of routes to routing tracks considering critical nets Power & Ground routing clock routing

Steiner Tree For a multi-terminal net Minimum spanning tree Large wire length Steiner tree A tree connecting all terminals and some additional nodes (Steiner nodes). Rectilinear Steiner Tree: Steiner tree such that all edges run horizontally and vertically Steiner Node

Routing is Hard Minimum Steiner Tree Problem: Challenges: Given a net, find the steiner tree with minimum length. Challenges: NP-Complete! May need to route millions of nets simultaneously without overlapping Obstacles may exist in the routing region.

Formal Problem Definition For delay consideration: Minimize diameter of net 10 5 10 D= 30 L= 30 D = 20 L= 30

Formal Problem Definition 2 1 2 1 D = 6 L = 7 D= 6 L = 6

Global Routing Global routing is divided into 3 phases: Region definition 2. Region assignment 3. Pin assignment to routing regions

Region Definition

Region Assignment (Global Routing) Cell 1 2

Pin Assignment Assign pins on routing region boundaries for each net. - Prepare for the detailed routing of each routing region. Cell 1 2

Detailed Routing Goal: Cell The actual wires are routed in the channel Produce the shortest wires and consume the least amount of space Cell 1 2

Region Definition Divide the routing area into routing regions of simple shape (rectangular): Channel: Pins on 2 opposite sides. 2-D Switchbox: Pins on 4 sides. 3-D Switchbox: Pins on all 6 sides. Switchbox Channel

Detailed Routing Types There are different detailed routers for different regions Switchbox router where the rectangle has pins on all four sides. Channel Router

Routing Regions 2D and 3D Switchboxes Bottom pin connection on 3D switchbox Metal5 Metal4 3D switchbox Top pin connection on cell Pin on channel boundary Horizontal channel 2D switchbox Metal3 Metal2 Metal1 Vertical channel

Routing Regions in Different Design Styles Gate-Array Standard-Cell Full-Custom Feedthrough Cell

Channel in Standard Cell Style Standard cell layout (Two-layer routing)

Routing Regions Gcells (Tiles) with macro cell layout Metal3 Metal2 etc.

Routing Regions Gcells (Tiles) with standard cells Metal1 (Standard cells) Metal3 Metal2 (Cell ports) Metal4 etc.

Routing Regions Gcells (Tiles) with standard cells (back-to-back) Metal3 Metal2 (Cell ports) Metal4 Metal1 (Back-to-back- standard cells) etc.

Routing in Different Design Styles Full-custom design Layout is dominated by macro cells and routing regions are non-uniform B F A C D E H V A B F D C E 1 2 3 4 5 5 B F A C D E 1 2 3 4 B F A C D E (1) Types of channels 5 4 3 2 1 (2) Channel ordering

Routing in Different Design Styles Standard-cell design If number of metal layers is limited, feedthrough cells must be used to route across multiple cell rows Feedthrough cells A A Variable-die, standard cell design: Total height = ΣCell row heights + All channel heights A A A

Routing in Different Design Styles Standard-cell design Steiner tree solution with minimal wirelength Steiner tree solution with fewest feedthrough cells

Switchbox Routed

Routing in Different Design Styles Gate-array design Cell sizes and sizes of routing regions between cells are fixed Available tracks Key Task: - Find a routable solution Unrouted net

Graph Modeling of Routing Regions Routing context is captured using a graph, where Nodes: Routing regions Edges: Adjoining regions Capacities: can be associated with both edges and nodes

Representations of Routing Regions Grid graph model 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ggrid = (V,E), where the nodes v  V represent the routing grid cells (gcells) and the edges represent connections of grid cell pairs (vi,vj)

Representations of Routing Regions Channel connectivity graph 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 G = (V,E), where the nodes v  V represent channels, and the edges E represent adjacencies of the channels

Representations of Routing Regions Switchbox connectivity (channel intersection) graph 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G = (V, E), where the nodes v  V represent switchboxes and an edge exists between two nodes if the corresponding switchboxes are on opposite sides of the same channel

Formal Problem Definition

Horizontal Routing Channel Channel Capacity Capacity: Number of available routing tracks or columns Two-layer routing: Multilayer routing: Horizontal Routing Channel B B C D B C B h dpitch A C A B B C D w s dpitch = s + w

Channel Capacity In practice: Grid lines are the same for all layers l: number of layers in a direction dpitch: size of largest pitch Example: two horizontal layers minimum wire width = 3 minimum wire spacing = 3 42

Pitch Size Models

Routing in Different Design Styles

Global Router Typical algorithm steps: Creating global router mesh Introduction ATLAS Basics ATLAS Plug-in Global Router ATLAS UIs AtlasDB ATLAS Engines Typical algorithm steps: Creating global router mesh Reading nets and pins Finding global and local nets Routing nets Length of nets Capacity of edges (Noise of nets)