Versatile Link FPGA-based Bit-Error-Ratio Tester for SEU-hardened Optical Links Csaba SOOS, Stéphane DETRAZ, Sérgio SILVA, Paulo MOREIRA, Spyridon PAPADOPOULOS, Ioannis PAPAKONSTANTINOU, Christophe SIGAUD, Pavel STEJSKAL, Jan TROSKA CERN, PH-ESE

Versatile Link Introduction ● Stringent requirements ● High speed, low power, high reliability, long lifetime etc. ● Harsh environment ● Noise, radiation etc. ● The answer: Versatile Link and GBT projects Csaba Soos et al. 2 TWEPP '09, September, 2009

Versatile Link Challenges (1/2) ● Amplitude noise ● Low-swing signals => reduced SNR ● Phase noise, i.e. Jitter ● Reduced bit period => less tolerance Csaba Soos et al. 3 TWEPP '09, September, 2009 Receiver electrical signalReceiver electrical signal, when the optical signal is attenuated

Versatile Link Challenges (2/2) ● Radiation effects ● Single-Event Upsets in the photodiode and in the receiver subassembly ● In the SEU dominated region, the BER is almost independent from the SNR Csaba Soos et al. 4 TWEPP '09, September, 2009 Jan Troska et al., “Single-Event Upsets in Photodiodes for Multi-Gb/s Data Transmission”, TWEPP 2008, Naxos, Greece

Versatile Link Test methods ● Eye diagram ● Good qualitative measurement ● Difficult to predict the bit error rate ● Used for mask tests (standards) ● Bathtub curve ● Links the jitter performance to the bit error rate ● Ignores the amplitude noise ● Not precise at low bit error rate (extrapolation) Csaba Soos et al. TWEPP '09, September,

Versatile Link Bit Error Rate testing ● Simple method for evaluating the performance of the entire transmission channel ● The measurement time depends on the required confidence level and the number of errors observed Csaba Soos et al. 6 TWEPP '09, September, 2009 T – measurement time BER – target bit error rate R – data rate CL – confidence level n – number of transmitted bits N – number of error bits

Versatile Link Motivations to build a custom BERT ● Limitations of the oscilloscope ● Sampling rate, memory, extrapolation, long measurement time ● We would like to use custom physical layer protocol (GBT) ● It will allow us to study the performance of the protocol ● Standard BERT uses pseudo-random bit pattern ● We would like to carry out tests on multiple channels ● It will reduce the overall test time ● Standard BERT can typically handle one channel at a time ● Error logging ● Required for off-line analysis ● Limited in standard BERT equipments Csaba Soos et al. TWEPP '09, September,

Versatile Link BERT system architecture PPC440 On-chip memory UART BERT core PLB0 DUT GBT RS232 Csaba Soos et al. 8 TWEPP '09, September, 2009 Crossbar External memory External memory PLB1 SoC implemented on the ML523 Virtex 5 transceiver evaluation platform

Versatile Link High-speed Serial 4.8 Gbit/s Bit Error Tester – Single Channel GBT Encoder MGT TX GBT Decoder MGT RX Error inject Compare Generator System errors Line errors GBT coreHard IP Control Csaba Soos et al. 9 TWEPP '09, September, 2009 DUT

Versatile Link Development platform ML523 Virtex 5 transceiver evaluation platform featuring: XC5VFX100T device - 8 GTX dual tiles - 16,000 slices DSP48E blocks - 8,208,000 bits internal memory MB DDR2 external memory Csaba Soos et al. 10 TWEPP '09, September, 2009

Versatile Link Test system electrical optical BERT Clock source Labview J-BERT N4903A Agilent 8156A Attenuator Power meter Agilent 8163B A Csaba Soos et al. 11 TWEPP '09, September, 2009

Versatile Link Graphical user interface - Labview Csaba Soos et al. 12 TWEPP '09, September, 2009 Stop criteriaMeasurement settingsResult plots Log file path

Versatile Link Measurement flowchart ● To improve speed, measurements are started from the highest attenuation value ● If a channel cannot acquire lock, it will be masked ● Stop criteria: target BER, confidence factor, time ● Record values: BER bounds, confidence factor, time, average optical power ● The loop is finished, when we reach the target BER on all channels Initialize Set attenuation Read counters Stop criteria ? Locked ? Write log End loop ? Csaba Soos et al. 13 TWEPP '09, September, 2009 N N Y Y N Y start end

Versatile Link Results – System and Line BER Csaba Soos et al. 14 TWEPP '09, September, 2009 High-speed Serial 4.8 Gbit/s GBT Encoder MGT TX GBT Decoder MGT RX Error inject Compare Generator System errors Line errors GBT coreHard IP Control DUT

Versatile Link Results – Scope vs. BERT Csaba Soos et al. 15 TWEPP '09, September, 2009

Versatile Link Future work ● Optimize the system for multi-channel readout ● FPGA resource usage (clock network and PLLs) ● Labview script ● Implement advanced logging ● Record erroneous words with timestamp ● Add support for multiple line rates ● Dynamic reconfiguration of the multi-gigabit transceivers ● Prepare the system for the SEU tests ● Test components in radiation Csaba Soos et al. 16 TWEPP '09, September, 2009

Versatile Link Conclusion ● Future, radiation-hard optical links will have to meet strict requirements ● The physical layer protocol will have to deal with the radiation induced errors (GBT) ● Bit-Error-Rate testing can be used to characterize the link components quantitatively ● Advanced testing (error logging) can provide insights into how error propagates in the system ● FPGA-based BERT system supporting the above mentioned features has been developed ● Link components are being tested in the lab, and will be tested soon (November 2009) in radiation Csaba Soos et al. 17 TWEPP '09, September, 2009

Versatile Link Thank You ! Csaba Soos et al. TWEPP '09, September,

Versatile Link System architecture – Virtex 4 GBT Bit Error Rate Tester GBT Bit Error Rate Tester PPC405 On-chip memory UART BERT core PLB JTAG Debug DUT GBT RS232 JTAG Csaba Soos et al. 19 TWEPP '09, September, 2009