32-BIT ADDER FOR LOW VOLTAGE OPERATION WITH LEVEL CONVERTERS PRIYADHARSHINI S

OBJECTIVES To reduce power consumption in a 32-bit adder circuit by reducing the voltage of operation To study the effect of voltage reduction on the delay of the circuit To identify an optimal voltage of operation at which the power-delay product is low To design a level converter to make the circuit compatible with other circuits 2

TOOLS USED ModelSim: To verify the functionality of the circuit Leonardo Spectrum: To synthesize the verilog gate level netlist MATLAB: To synthesize the netlist compatible with PowerSim Design Architect: To obtain the transistor level design of gates LTSpice: To evaluate the delays of individual gates PowerSim: To assess the performance of the circuit at different voltages 3

VHDL behavioral file (adder.vhd) Leonardo Spectrum Verilog gate level netlist – 180nm (adder.v) MATLAB conversion code Rutgers Mode compatible netlist (adder.myrutmod) Input vectors file (generated by randomgen.cpp) Technology file 45nm Powersim (executable file from.cpp files) Delay file (.randlf) Gate-wise simulation in LTSPICE Outputs ModelSim (functional verification) PowerSim Tutorial – Manish Kulkarni 4

LOW VOLTAGE OPERATION I = K (V GS - V T ) 2 / 2 R α 1/I Resistance increases as voltage reduces Time constant = RC Delay increases as voltage decreases 5 0V

LOW VOLTAGE OPERATION Dynamic Power = αCV 2 Dynamic Power reduces with voltage reduction Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8 tmlhttp:// tml - Lecture 4 Power Dissipation of CMOS circuits 6

POWER CALCULATION Dynamic power α V 2 f Power = kV 2 /T At a voltage of 1.1 V (normal operation) ▫Dynamic power = µW ▫T = 650 ps ▫=> k = p mho Power = V 2 /T pW 7

DELAY CALCULATION Delay = K V/ (V – V th ) α At 1.1 V, Delay = 625 ps At 1.0 V, Delay= 640 ps ▫K = 420 ps ▫α = 0.73 Delay = 420 V/ (V – V th ) 0.73 Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8 8

DYNAMIC POWER in adder circuit(µW) From Simulation Calculated value % decrease in power 1.1 V V V V V V V V

DELAY in adder circuit (ps) From Simulation Calculated value % increase in delay 1.1 V V V V V V V V

CIRCUIT SETUP 11 ADDER CIRCUIT VDD_L LOW TO HIGH CONVERTER VDD_LVDD_H HIGH TO LOW CONVERTER VDD_H VDD_L

HIGH TO LOW converter – not required V Can turn off PMOS and can turn on NMOS 0.5V 1.1 V Will not turn off PMOS V GS < V th for PMOS to be turned on V thp = V

LEVEL CONVERTER 13

LEVEL CONVERTER OPERATION 14 Level Converter for CMOS 3V to from 5V United States Patent [19] Masaki et al. Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997

RESULTS 1.1 V1.0 V0.9 V0.8 V0.7 V0.6 V0.5 V0.4 V Average power (µW) Power per converter (nW) Total power (µW) %decrease in power Adder delay (ps) Converter delay (ps) Total Delay (ps) %increase in delay Power-Delay product (pWs) Number of gates in adder =128 Approximate increase in area = 25.78%

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CONCLUSION The adder circuit can be operated at 0.5V in order to minimize power Parameters other than power-delay product should be considered to decide on the operating voltage 17

FUTURE WORK Evaluating performance of circuit with a few chains of gates operating at low voltages Lowering power by introducing low-threshold transistors in non-critical paths 18

REFERENCES Gonzalez, R., Gordon, B.M., Horowitz, M.A., Supply and Threshold Voltage Scaling for Low Power CMOS, IEEE Journal of Solid-State Circuits, Aug 1997, Volume 32, Issue 8 Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low- Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, Volume 27, No.4, April 1992 Masaki et al., Level Converter for CMOS 3V to from 5V, United States Patent [19] Patent Number: 5,680,064 Date of Patent: Oct. 21, 1997 Kiat-Seng Yeo, Kaushik Roy, Low-Voltage, Low-Power VLSI Subsystems, McGraw Hill Class lectures 19

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