Study of 60GHz Wireless Network & Circuit Ahn Yong-joon

Contents Simulation and Measurement of ‘MM-Wave CMOS Design’ Simulation and Measurement of ‘Algorithmic Design of CMOS LNAs and Pas for 60GHz Radio’

MM-Wave CMOS Design CPW Filter - 30GHz Band Pass Filter - Don’t do special modeling of bend and junction Insertion Loss Output Return Loss

MM-Wave CMOS Design Junctions and Bends are not critical Size is 0.93mm*0.64mm

MM-Wave CMOS Design Amplifier Design - 40GHz & 60GHz Amplifier - Size : 1.3mm*1.1mm & 1.3mm*1.0mm - Both 25% Bandwidth - Three stage of cascode device

MM-Wave CMOS Design - Only bias current & length of T-lines are different - Cascode  reduce Miller eff.  High freq range - Cascode Transistor.  40GHz 60GHz bias 100uA/um 150uA/um MAG 8.9dB 6.0dB - Lengths of All T-lines < λ/4

MM-Wave CMOS Design Insertion Loss - Interstage matching network : 40GHz  2.5dB 60GHz  1.8dB - Input matching network : 40GHz  1.6dB 60GHz  1.3dB - Output matching network : 40GHz  2.0dB 60GHz  1.6dB  because shorter T-line

MM-Wave CMOS Design Measurement of Amps a) Measurement setup - [12] de-embededing & [20] DUT measure On Wafer...

MM-Wave CMOS Design Result of 40GHz - Peak Power gain : 19dB - Return losses > 15dB - 3-dB Bandwidth 34-44GHz - Reverse isolation 50dB up to 65GHz - Output P1dB -0.9dBm - IIP3 -7.4dBm - NF N/A - 24mA with 1.5V

MM-Wave CMOS Design Result of 60GHz LNA - Peak Power gain : 12dB - Return losses > 15dB - 3-dB Bandwidth 51-65GHz - Reverse isolation 45dB up to 65GHz - Output P1dB +2.0dBm - IIP3 N/A - NF 8.8dB - 36mA with 1.5V

MM-Wave CMOS Design [5] : The designs and optimizations are based on device S-parameter measurements & use MSL [4] : also use MSL

MM-Wave CMOS Design Measured NF is higher than simulation result  about 2dB BSIM3 noise model is not properly  such as short channel noise or induced gate noise Need to use more advanced RF transistor model

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio 60GHz LNA Result - Not de-embeded model - Peak Gain 58GHz (Sim. : 62.4GHz) - S11 & S22 < -6dB 55-65GHz (Sim : < -10dB 50-65GHz) - Result is downshifted from simulation.  Lack of RC parasitic extraction tool.  L G is overestimated

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio - Isolation > 32dB - IIP3 : -6.8dBm - NF : N/A (Lack of a down convert mixer) 4.5dB (Simulated result)

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio Higher gain, Lower NF, Lower Power diss, smaller area.

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio Result of 60GHz PA - Peak Power gain : - Return losses > 15dB - 3-dB Bandwidth 13GHz (52-65GHz) - S11<-10dB (51-65GHz) S22<-10dB (60-65GHz) - Output P1dB +6.4dBm - Psat 9.3dBm - Bias current 0.28mA/um

Algorithmic Design of CMOS LNAs and PAs for 60GHz Radio

Scaling from 130nm to 90nm better performance: - Lower noise (comparable to F t /F MAX LNAs) - Lower power dissipation - Higher gain (in LNAs) - Reasonable output power and gain for PA