DDL hardware, DATE training1 Detector Data Link (DDL) DDL hardware Csaba SOOS

DDL hardware, DATE training2 Readout system Front-end electronics Detector Data Links DDL SIU DDL DIU RORC Source Interface Unit Destination Interface Unit Read Out Receiver Card LDC Local Data Concentrator Front- End Digital Crate/Computer P2 Cavern P2 Access shaft Optical Fibre ~200 meters

DDL hardware, DATE training3 DDL architecture Source Interface Unit (SIU) (1) –Interface to the Front-end Electronics (2) Destination Interface Unit (DIU) (3) –Interface to the Readout Receiver Card (4) Full duplex optical link (5) –Multimode optical cable of up to 200 m

DDL hardware, DATE training4 DDL hardware

DDL hardware, DATE training5 DDL interfaces SIU-FEE interface –3.3V (LVTTL) interface –32-bit wide half-duplex data bus (bi-directional bus) –Bi-directional flow control –User defined clock (synchronous interface) –JTAG interface DIU-RORC interface –3.3V (LVTTL) interface –32-bit wide full-duplex data bus –Bi-directional flow control –User defined clock (synchronous interface)

DDL hardware, DATE training6 SIU-FEE interface fbD(31..0)- data lines(bi-directional) fbTEN_N- data enable(bi-directional) fbCTRL_N- data qualifier(bi-directional) fiDIR- bus direction(FEE input) fiBEN_N- bus enable(FEE input) fiLF_N- link full(FEE input) foBSY_N- front-end busy(SIU input) foCLK- interface clock(SIU input) TAP_TCK- JTAG clock(FEE input) TAP_TDI- JTAG data in(FEE input) TAP_TDO- JTAG data out(SIU input) TAP_TMS- JTAG mode select(FEE input) TAP_TRST- JTAG reset(FEE input)

DDL hardware, DATE training7 DIU-RORC interface riD(31..0)- data lines(RORC input) riTEN_N- transfer enable(RORC input) riSTS_N- data qualifier(RORC input) riLF_N- link full(RORC input) riLD_N- link down(RORC input) roD(31..0)- data lines(DIU input) roTEN_N- transfer enable(DIU input) roCMD_N- data qualifier(DIU input) roBSY_N- RORC busy(DIU input) roRST_N- DIU reset(DIU input) roCLK- interface clock(DIU input)

DDL hardware, DATE training8 Link management idle off-line on-line DIUSIURORC Power-on SIU reset Reset Link up SIU reset Offline Online Offline Online on-line

DDL hardware, DATE training9 Front-end control on-line FECTRL CTSTW on-line DIUSIURORC Online FEE command Report FEE FEE control idle foCLK fiBEN_N fiDIR FECTRL fbD fbTEN_N fbCTRL_N

DDL hardware, DATE training10 Front-end status read on-line FECTRL FESTW on-line DIUSIURORC Online FEE command Status and report FEE FEE status read CTSTW foCLK fiBEN_N fiDIR FESTRD fbD fbTEN_N fbCTRL_N HiZ foCLK fiBEN_N fiDIR FESTW fbD fbTEN_N fbCTRL_N HiZ

DDL hardware, DATE training11 Event read on-line RDYRX CTSTW DIUSIURORC Online FEE command Report FEE RDYRX CTSTW FEE data EOBTR data blocks Event data FEE command Report EOBTR Flow control foCLK fiBEN_N fiDIR RDYRX fbD fbTEN_N fbCTRL_N HiZ foCLK fiBEN_N fiDIR EOBTR fbD fbTEN_N fbCTRL_N HiZ

DDL hardware, DATE training12 Block write on-line STBWR CTSTW DIUSIURORC Online FEE command Report FEE STBWR CTSTW FEE data EOBTR FEE command Report EOBTR Flow control Block data data block foCLK fiBEN_N fiDIR fbD fbTEN_N fbCTRL_N foBSY_N EOBTRDn-1Dn

DDL hardware, DATE training13 Block read on-line STBRD CTSTW DIUSIURORC Online FEE command Report FEE STBRD CTSTW FEE data EOBTR data block Block data FEE command Report EOBTR Flow control foCLK fiBEN_N fiDIR STBRD fbD fbTEN_N fbCTRL_N HiZ foCLK fiBEN_N fiDIR EOBTR fbD fbTEN_N fbCTRL_N HiZ

DDL hardware, DATE training14 PCI RORC

DDL hardware, DATE training15 D-RORC

DDL hardware, DATE training16 RORC features Interface between the DIU and PCI local bus –pRORC: 32 bit/33 MHz PCI version, max. throughput 132 MB/s –D-RORC: 64 bit/66 MHz PCI version, max. throughput 528 MB/s PCI master capability, data push architecture –Autonomous operation with little software assistance –Supports multi-paged memory management Direct data transfer to the PC memory –No local memory on the board –Small elasticity buffers between different clock domains Built-in test capability –Internal pattern generator can produce formatted data

DDL hardware, DATE training17 The Free FIFO PRORC PC memory bank Firmware readout page address Free FIFO PC CPU Allocation of free pages

DDL hardware, DATE training18 Direct Memory Access PRORC Firmware PC memory bank DDL No involvement PC CPU

DDL hardware, DATE training19 The Ready FIFO PRORC PC memory bank readout DDL Ready FIFO Firmware addresspage status addresspage status addresspage status Delivery of filled pages PC CPU

DDL hardware, DATE training20 Test equipments Front-end Emulator Interface Card (FEIC) –Fully functional hardware to emulate the detector front-ends –Formatted data block generation –Internal (free running) or external (pulse) triggering capabilities –Adjustable parameters (using front-end control) –Operates at the nominal speed of the DDL Source Interface Unit Simulator (SIMU) –Simulates the behavior of the DDL without any additional hardware –Eases the development and the hardware debugging –Size is similar to the real SIU