Emerging Technologies: A CompSci Perspective UC SANTA BARBARA Tim Sherwood

Software Beware

The End of an Era $381B / year

The Beginning of a New Era 80 Cores Integrated MEMS 3D Stacks of Dies

The Role of Architecture Applications Runtime System Architecture Circuit Device Package SW HW Constraints Demands Emerging Technology (Noise, Thermal, Yield) (Battery Life, Performance, Programmability )

temp package total power dynamic power V utilized area communication A Simple Performance “Ecosystem” parallelismfreq leakage app OS or runtime feedback chip performance No multicore, no spatial variance, no temporal variance, no metrics of cost or error or yield

3D Integration 80 Cores Integrated MEMS 3D Stacks of Dies

3d technology Through Silicon Vias (TSV) 5x5μm Standard Si Substrate CMP Reduced Si Layer active layer Science Fiction?  Intel, IBM, Ziptronix invest heavily in 3d integration research  Many demonstrated 3d prototype systems

Work at UCSB Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood. Introspective 3D Chips, Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems ( ASPLOS ), October San Jose, CA Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee. A Thermally- Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy, Proceedings of the 43nd Design Automation Conference ( DAC ), June San Francisco, CA

Basic Savings in 3D Area: 4 Dist: √8 ≈ 2.8 Area: 2 Dist: √4 ≈ 2 + 1L Area: 1 Dist: √2 ≈ L BW: √8 ≈ 2.8 BW: 2√4 ≈ 4 BW: 4√2 ≈ 5.6 On-chip Latency improved Bandwidth could improve even more UCSB First to Successfully Model Thermal/Performance

Addressing more than Performance The hardware/software boundary is uniquely situated  Ultimately, Everything is an instruction  Used by Intel, AMD, Freescale, to guide their development Could Provide Unprecedented Visibility  Not just data capture, we need the ability to put together a cohesive picture of system interactions and correlate between them in a sound and non-intrusive manner

Cutting Through Abstraction Complex interactions across levels of abstraction make debugging, optimizing, securing, and analysis in general difficult

To Integrated Monitoring Hardware L1_BPU Decode Trace Cache Top L2_BPU Bus Control MOBITLB Trace Cache Bottom DTLB L1 Cache Top L2 Cache L1 Cache Bottom FP Exec UROM FP Reg Alloc Rename Instr Q1 Sched Instr Q2 Int Reg Retire Int Exec Mem Ctl What programmers want 32 bit Memory Address 32 bit Memory Value 10 bit Opcodes 2, 5 bit Register Names 2, 32 bit Register Values 10 bits of “status” 3x 4x 1892 bits per cycle = 1 4Ghz Less buggy systems ($54 Billion / Year )

Why programmers cant have it Interconnect is not free  Huge cross chip busses  OptBuf 285um  20,000 buffers Analysis is not free  Significant processing required Extra cost of added heat  $15 budget for cooling Used by developers To Integrated Monitoring Hardware L1_BPU Decode Trace Cache Top L2_BPU Bus Control MOBITLB Trace Cache Bottom DTLB L1 Cache Top L2 Cache L1 Cache Bottom FP Exec UROM FP Reg Alloc Rename Instr Q1 Sched Instr Q2 Int Reg Retire Int Exec Mem Ctl

3D Introspection Primary Processor 5x5μm Standard Si Substrate CMP Reduced Si Layer active layer Observer

Thermal Impact w/ 4x Processingw/ 8x ProcessingP4 – Base Case Processing Layer w/ 3D Layer Analysis Layer

Conclusions Emerging Technologies will play a significant new role  Risk is hard to avert right now UCSB Computer Science and Engineering  Collaborate across disciplines to consider the entire SW/HW Research that is driving industry  UCSB Technology in use in most Microprocessors and Networks  Always looking for more collaboration with industry partners

NSF CNS , NSF CCF , NSF CCF