1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 4 Computing Platforms.

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Presentation transcript:

1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 4 Computing Platforms

2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.1 Hardware architecture of a typical computing platform.

3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.2 Software layer diagram for an embedded system.

4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.3 Organization of a bus.

5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.4 The four-cycle handshake.

6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.5 A typical sequence diagram for bus operations.

7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.6 Timing diagram notation.

8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.7 Timing diagram for read and write on the example bus.

9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.8 A wait state on a read operation.

10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.9 A burst read transaction.

11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.10 State diagrams for the bus read transaction.

12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.11 A bus with a DMA controller.

13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.12 UML sequence of system activity around a DMA transfer.

14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.13 Cyclic scheduling of a DMA request.

15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.14 A multiple bus system.

16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.15 UML state diagram of bus bridge operation.

17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.16 Elements of the ARM AMBA bus system.

18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.17 Organization of a basic memory.

19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.18 An SDRAM read operation.

20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.19 The memory controller in a computer system.

21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.20 Channels and banks in a memory system.

22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.21 A BeagleBoard.

23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.22 An ARM evaluation module.

24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.23 Connecting a host and target system.

25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.24 Architecture of a logic analyzer.

26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.25 Use case for playing multimedia.

27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.26 Use case of synchronizing with a host system.

28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.27 Hardware architecture of a generic consumer electronics device.

29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.28 Platform-level data flows and performance.

30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.29 Times and data volumes in a basic bus transfer.

31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.30 Times and data volumes in a burst bus transfer.

32 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.31 Memory aspect ratios.

33 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.32 Front panel of the alarm clock.

34 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.33 Class diagram for the alarm clock.

35 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.34 Details of user interface classes for the alarm clock.

36 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.35 The Mechanism class.

37 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.36 State diagram for update-time.

38 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.37 State diagram for scan-keyboard.

39 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.38 Preprocessing button inputs.

40 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.39 MPEG Layer 1 encoder.

41 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.40 MPEG Layer 1 data frame format.

42 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.41 MPEG Layer 1 decoder.

43 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.42 Requirements for the audio player.

44 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.43 Classes in the audio player.

45 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.44 State diagram for file display and selection.

46 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.45 State diagram for audio playback.

47 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 4.46 Architecture of a Cirrus audio processor for CD/MP3 players.

48 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 4.1

49 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 4.2

50 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 4.3

51 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure4.4

52 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 4.5

53 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 4.6