Placement by Simulated Annealing

Simulated Annealing  Simulates annealing process for placement  Initial placement −Random positions  Perturb by block exchanging  If Δcost < 0,  accept  otherwise, may still accept if const increase is not too much −Too much increase? −Depends on the algorithm stage 2

3 Search Space Cost  Avoids getting trapped in local minimum

4 Input: set of all cells V Output: placement P T = T 0 // set initial temperature P = PLACE(V)// arbitrary initial placement while (T > T min ) while (!STOP())// not yet in equilibrium at T new_P = PERTURB(P) Δcost = COST(new_P) – COST(P) if (Δcost < 0)// cost improvement P = new_P// accept new placement else// no cost improvement r = RANDOM(0,1)// random number [0,1) if (r < e -Δcost/T )// probabilistically accept P = new_P T = α ∙ T// reduce T, 0 < α < 1 Simulated Annealing – Algorithm

Temperature Reduction Function 5

Cost Decrease 6

SA Parameters Quality of result depends largely on parameters:  Initial Temperature  Final Temperature  Stop Criterion  Cooling Schedule  Move (Perturb) Function  Cost Function 7

VPR Package  V. Betz and J. Rose, “VPR: A new packing, placement and routing tool for FPGA research,” International Workshop on Field-Programmable Logic and Applications,  J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, M. Fang, and J. Rose, “VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling,” in Int’l Symp. on Field-Programmable Gate Arrays, Feb. 2009, pp. 133–142.  VPR 5.0,  VPR 6.0, Beta Release, May 30,

Placement can Make A Difference MCNC Benchmark circuit e64 (contains LUT). Placed to a FPGA. Random Initial Placement Final Placement After Detailed Routing 9

TimberWolf Package  Based on simulated annealing  Handles both placement and routing Design styles:  gate-array,  standard-cell  macrocell 10

TimberWolf Gate-Array Placement State:  An assignment of the gates to the gate positions. Move  Interchange 2 gates, OR  Move a gate to a vacant position. Cost Function  Total wire length estimation  Congestion 11

Cooling Schedule  Initial temperature: 4x10 6  Final temperature:

ITools Variable die 33% smaller Translator, Floorplanner, Standard Cell Placer, Gate Array Placer, Global Router & Detail Router 13

TimberWolf for Standard Cell Perturbs:  Move  Swap  Mirror around y-axis 14

Range Limiter  What pairs of modules can be interchanged? Range Limiter for Move:  At the beginning, (W T, H T ) is very large −big enough to contain the whole chip.  Window size shrinks slowly as the temperature decreases. −Height and width  log(T).  Stage 2: window size is so small −No inter-row module interchanges are possible. 15

TimberWolf for Standard Cell Stage 1 (at high temperature):  Move cells between different rows as well as within the same row.  Allow overlapping of cells.  Minimize the total wire length, cell overlapping, and differences in row lengths. Stage 2 (at low temperature):  Remove overlapping from the solution of Stage 1.  Exchange adjacent cells.  Minimize total wire length. 16

Cost Function xspan yspan 17

18 Advantages:  Can find global optimum (given sufficient time)  Well-suited for detailed placement Disadvantages:  Very slow  To achieve high-quality implementation, laborious parameter tuning is necessary  Randomized, chaotic algorithms - small changes in the input lead to large changes in the output Practical applications of SA:  Small placement instances with complicated constraints  Detailed placement, where SA can be applied in small windows  FPGA layout, where complicated constraints Simulated Annealing

Tabu Search  From a solution s, find a set of solutions in this neighborhood N(s). Tabu List (T):  Recently tried movements −To avoid loop.  Select a solution from N(s) – T with minimum cost. 19

Probabilistic Congestion Estimation  M. Saeedi, M. Saheb Zamani, A. Jahanian, “Evaluation, prediction and reduction of routing congestion,” Microelectronics Journal, Elsevier,

Channelless Standard Cell 21

Probabilities The probability of a v-bend path from bin (i, j) to bin (n,m) to pass through the horizontal/vertical track (x, y). 22

Stataistics 23

Congestion Estimation The number of all possible paths from bin (i,j) to bin (n,m) which pass through the horizontal/vertical track in bin (x,y) : The number of all possible paths from bin (i,j) to bin (n,m) 24

Congestion Map 25