1. EDA Lab., Tsinghua University
Recursively Combine Floorplan and Q-Place in Mixed Mode Placement Based on Circuit‘s Variety of Block Configuration
Changqi Yang, Xianlong Hong, Hannah Honghua Yang
CS, Tsinghua University
Strategic CAD Labs, Intel Corporation
2/16/2019
EDA Lab., Tsinghua University

2. EDA Lab., Tsinghua University
Content
Motivation
Previous Works
Recursive Design Flow
Algorithms for Each Stage
Experimental Results
Future Work
The content of our presentation is listed as following: first, we will introduce the motivation about our work. After briefly discussing the previous work, we will introduce the recursive design flow in MMP. Then, algorithms for each design stage will be described. The final parts include the experimental results and our future work
2/16/2019
EDA Lab., Tsinghua University

3. EDA Lab., Tsinghua University
Motivation(1)
Integrating more circuit cells into one chip results in MMP(Mixed Mode Placement) problem:
Large scale: vast amount of cells.
Mixed mode: standard cells mixed with blocks to be placed simultaneously.
Floorplan and Placement technology
Floorplan: can obtain overlap-free layout but is the great time-consumer.
Placement: especially Q-Place, can obtain results rapidly, but it is difficult for eliminating overlap between standard cells and blocks.
As we have known, because of SOC, Integrating more circuit cells into one chip results in MMP(Mixed Mode Placement) problem. There are two unique features in MMP: first is its large scale. Generally said, the number of cells is very vast. The other feature is that standard cells mixed with blocks should be placed simultaneously, this is so-called mixed mode. Currently, there are two main categories of placement algorithms: floorplan and placement. Floorplan can obtain overlap-free layout but it is the great time-consumer. And Placement, especially Q-Place, can obtain results rapidly, but it is difficult for eliminating overlap between standard cells and blocks.
2/16/2019
EDA Lab., Tsinghua University

4. EDA Lab., Tsinghua University
Motivation(2)
The common solution is the combination of floorplan and Q-Place according to circuit hierarchy.
Another challenge for MMP is the variety of circuit:
The number of blocks varies from 2 to 424
The size of blocks varies from 57 to 2045
Circuits
#cells
#macro
blocks
#nets
Block area (average)
/cell area(average)
block2
7094 2
10049
2045
block6
5996 6
872
block8
5662 8
695
block9
5895 9
751
block10
5151 10
676
ibm01
12260
246
14111 57
ibm02
19071
271
19584
157
ibm11
69779
373
81454
166
ibm13
83285
424
99666
162
The common approach for solving MMP problem is to combine floorplan and placement together according to circuit hierarchy. However, there is still another challenge for MMP. It is the variety of circuit. Here, the variety of circuit is limited to the fact that the number and the size of blocks are much different in different circuits. Here is the table of characteristics for our test cases. Obviously, the number of blocks varies from 2 to 424, and the size of blocks varies from 57 to 2045 which is evaluated by the ratio of average block area and average cell area.
2/16/2019
EDA Lab., Tsinghua University

5. EDA Lab., Tsinghua University
Previous Works
HMMP: presented by W.M Wu in ASICON2001
Generate two-level hierarchy of circuit.
Floorplan on block-level and Q-Place on cell-level.
Fit the block configuration of few but huge blocks.
Fall into the trap of running out of time in floorplan when there are too many blocks in circuit.
MPG-MS presented by J. Cong in ASP-DAC03
Generate multi-level hierarchy.
Bin-Based floorplan is adopted recursively on each level.
Fit the block configuration of numerous blocks
Consume much time because of its Simulated Annealing Process with high time complexity.
In the previous work, W.M.Wu presented an algorithm named HMMP in ASICON2001. In his paper, the algorithm generates two-level hierarchy of circuit and then adopts floorplan algorithm on block-level which is followed by the Q-place on cell-level. His approach can fit the block configuration of few but huge blocks. However, it will fall into the trap of running out of time in floorplan when there are too many blocks in circuit. J.Cong presented a multi-level algorithm named MPG-MS for MMP. In his approach, multi-level hierarchy is generated and the bin-based floorplan is adopted recursively on each level. It can fit the block configuration of numerous blocks. But it will consume much time because of its simulated annealing process with high time complexity.
2/16/2019
EDA Lab., Tsinghua University

6. Recursive Design Flow(1)
The presented design flow RMMP completes placement through 3 routines: partition, global placement and detailed placement.
In partition phase, the components and netlist of circuit are analyzed and partitioned recursively to construct a tree of virtual blocks with the root pointing to the whole circuit on the chip.
An operation-selector will travel along through all the nodes of the tree in the order of Deep First Search (DFS).
For the virtual block composed by physical blocks or by child virtual blocks, the selector performs a fixed-outline floorplanner
Otherwise, it performs a Q-Place based placer.
Our design flow named RMMP for MMP is based on recursive partitioning. It completes placement through 3 routines: partition, global placement and detailed placement. In partition phase, the components and netlist of circuit are analyzed and partitioned recursively to construct a tree of virtual blocks with the root pointing to the whole circuit on the chip. An operation-selector will travel along through all the nodes of the tree in the order of Deep First Search (DFS). For the virtual block composed by physical blocks or by child virtual blocks, the selector performs a fixed-outline floorplanning. Otherwise, it performs a Q-Place based placer.
2/16/2019
EDA Lab., Tsinghua University

7. Recursive Design Flow(2)
physical block
standard cell
Partition
Floorplan
Q-Place
Detailed Placement
virtual block
This is the figure of our design flow. The cells are organized as tree of virtual blocks. And partition, floorplan, Q-place are performed on different nodes respectively.
2/16/2019
EDA Lab., Tsinghua University

8. EDA Lab., Tsinghua University
Algorithms(1)
Partition
Use a bottom up cluster algorithm to create clusters each of which consists of no more than C standard cells: C-control parameter
Use a top down partition algorithm to create partitions
For each of its virtual blocks, involve partition process recursively
For the partition stage, we Use a bottom up cluster algorithm to create clusters each of which consists of no more than C standard cells. Here C is the control parameter which can control the size of clusters. Then we Use a top down partition algorithm to create partitions and convert all partitions into virtual blocks. For each of its virtual blocks, partition process is involved recursively.
2/16/2019
EDA Lab., Tsinghua University

9. EDA Lab., Tsinghua University
Algorithms(2)
Global Placement
The global placement is the combination of a floorplanner and a Q-Placer which are performed in the charge of an operation selector.
Fixed-Outline Floorplanning
=WL*Len+WR1*Max(ChipX-PX,0)+WR2*Max(ChipY-PY,0), where Len is the total net length, PX and PY are width and height in packing, ChipX and ChipY are width and height of the chip, wL and wR1 as well as wR2 are weighting factors.
CBL – representation of encode for block placement.
the area packed by blocks does not have to be minimized as an objective
Our global placement consists of two sub-algorithms: a fixed-outline floorplanning and a Q-Place. They are performed in the charge of an operation selector. Because the floorplanning is done within a fixed area, the area packed by blocks does not have to be minimized as an objective. Therefore, we use the following equation as the objective in floorplanning. Here Len is the total net length, PX and PY are width and height in packing, ChipX and ChipY are width and height of the chip, wL and wR1 as well as wR2 are weighting factors. CBL is adopted as the representation of encode for block placement and the optimization process is based on Simulated Annealing Process.
2/16/2019
EDA Lab., Tsinghua University

10. EDA Lab., Tsinghua University
Algorithms(3)
Q-Place
The objective function is the minimization for the total wire length:
The constraints make the cells distribute on the chip evenly
A faster and more stable method FaSa based on Lagrange multipliers to solve the linear constraint quadratic programming problem
For the Q-Place, The objective function is the minimization for the total wire length. We use the following constraints which can make the cells distribute on the chip evenly. A faster and more stable method FaSa based on Lagrange multipliers to solve the linear constraint quadratic programming problem. So our solution is stable and effective.
2/16/2019
EDA Lab., Tsinghua University

11. EDA Lab., Tsinghua University
Algorithm(4)
Detailed Placement: After global placement in all virtual blocks, all standard cells and original blocks are placed near their optimum locations. Detailed placement is adopted throughout the whole chip with original blocks aligned to rows previously.
An initial detailed placement is obtained by inheriting cell positions determined by global placement procedure.
Row assignment refining and row evening are interlaced to reduce the wire length in y and x directions respectively, while rows evening and overlap removing are also done within interlaces.
The wire length is reduced further by cell permutation within rows.
After global placement in all virtual blocks, all standard cells and original blocks are placed near their optimum locations. Detailed placement is adopted throughout the whole chip with original blocks aligned to rows previously. There are 3 steps to complete the detailed placement: first, An initial detailed placement is obtained by inheriting cell positions determined by global placement procedure; second, Row assignment refining and row evening are interlaced to reduce the wire length in y and x directions respectively, while rows evening and overlap removing are also done within interlaces. Finally, The wire length is reduced further by cell permutation within rows.
2/16/2019
EDA Lab., Tsinghua University

12. Experimental Results(1)
Circuits
#cells
#macro
blocks
#nets
Block area (average)
/cell area(average)
block2
7094 2
10049
2045
block6
5996 6
872
block8
5662 8
695
block9
5895 9
751
block10
5151 10
676
ibm01
12260
246
14111 57
ibm02
19071
271
19584
157
ibm11
69779
373
81454
166
ibm13
83285
424
99666
162
In our experiments, we test different cases. The characteristics about these cases are shown in this table. We have seen it in previous slide.
2/16/2019
EDA Lab., Tsinghua University

13. Experimental Results(2)
RMMP VS HMMP
Circuits
HMMP
RunTime (s)
RMMP
RunTime(s)
WireLen
(um)
Impr
(wl %)
block2
358
320
1.692e6
1.662e6
1.74
block6
382
335
2.029e6
1.556e6
23.30
block8
405
314
2.022e6
1.522e6
24.74
block9
388
295
2.345e6
2.216e6
5.5
block10
356
2.131e6
1.376e6
35.4
First, we compare our algorithm RMMP with HMMP presented before. The running time is comparable. But, the wire length is reduced much. The significant improvement is up to 35% on some case.
2/16/2019
EDA Lab., Tsinghua University

14. Experimental Results(3)
RMMP VS MPG-MS
Circuits
MPG
WireLen
(um)
RMMP
RunTime
(min)
Impr
(time %)
ibm01
3.01e6
3.16e6 18 11 39
ibm02
7.42e6
6.59e6 32 44
ibm11
2.65e7
2.96e7
112 82 27
ibm13
3.77e7
3.94e7
151
105 30
Secondly, we compare RMMP with MGP-MS we mentioned before. Because of the combination of floorplan and Q-place, our approach is much faster than MGP-MS. The improvement about speed can reach 30%-40%. However, the wire length in RMMP is kept comparable as that in MGP-MS.
2/16/2019
EDA Lab., Tsinghua University

15. EDA Lab., Tsinghua University
Future Work
Improve algorithms for each stage.
Support polygon in block floorplan
Support placement in rectilinear-region
Optimum timing delay in MMP.
In our future work, we will improve algorithms for each stage of MMP design flow. For example, we will support polygon in block floorplan and support placement in rectilinear-region. And, our previous work was taking wire length as the objective of optimization which is not enough. We will optimum timing behavior in MMP which has great challenges.
2/16/2019
EDA Lab., Tsinghua University

16. EDA Lab., Tsinghua University
Thank you
2/16/2019
EDA Lab., Tsinghua University