Implementation of Test Engineering Training using Remote ATE: A First Experience at European Level Yves Bertrand, Marie-Lise Flottes, LIRMM Montpellier Hans-Joachim Wunderlich, Nicoleta Pricopi, Universität Stuttgart

Test theory vs. Test practice Industrial World Academic World ATE Shmoo Wafer Sort Binning . . . Fault Modelling Fault Simulation ATPG DFT BIST . . . Bridging the Gap First I have to situate the problem of education in the field of IC Test And the first think I have to do is to present the state-of-the-art in IC manufacturing Here is the photograph of a Bull Microprocessor which may be considered as a representative Integated Circuit of nowaday manufacturing This IC contains about 7 millions of transistors Implemented on a 2x2 cm2 silicon chip With 428 I/O pins Now what are the problems we have to face when testing such a circuit 23.03.2003 Testmethoden in der Ausbildung

European Project: EuNICE-Test Objectives and focus To strengthen in critical disciplines of design and test in microelectronics leading education centres, with the active support of industry To address shortage of skills in the microelectronics industry by encouraging students at pre- and post-doctoral level to carry out innovative research, supported by industry 23.03.2003 Testmethoden in der Ausbildung

Remote access to central test ressources Stuttgart Ljubljana Renater Torino Barcelona 23.03.2003 Testmethoden in der Ausbildung

Testmethoden in der Ausbildung Test Tool Agilent 83000-F330t Per-Pin Architecture Pin Count: 128 (/512) Max. Speed: 330MHz PMU/16 Pins Analog Resources The evolution of IC's manufacturing shows that, proportionnally , the number of Transistors increases much more than the number of Pins This obviously induces a very important loss in acceeding the internal nodes And this makes the test of IC's more and more difficult Also, due to the telecom and multimedia market explosion there is an increasing production of circuits that implements on the same chip digital and analog blocks And the test of these so-called "mixed-circuits" is a very difficult task In the same time the comptiveness of the IC market implies Quality requirements and, consequently, a better binning at the end of production lines All these arguments make that the test is a real key point when developping and producing a new IC. As an example to illustrate the financial impact of the test problem, know that the test part may represent up to 20% of the global cost of a complex mixed-signal circuit 23.03.2003 Testmethoden in der Ausbildung

Testmethoden in der Ausbildung Test Tool (2) New ATE : Agilent 93000 SOC Tester Data rates up to 1 Gbit/s Up to 960 digital pins plus integrated analog instrument Up to 32 analog instruments Flexible, scalable test platform SmarTest software environment 23.03.2003 Testmethoden in der Ausbildung

Testmethoden in der Ausbildung Implementation Barcelona Stuttgart Torino Ljubljana Test Server Tester CRTC, Montpellier 23.03.2003 Testmethoden in der Ausbildung

Testmethoden in der Ausbildung Test Resources CRTC Test Resources 83K/93K Agilent Testers Technical Staff : 1 Test Engineer (+ network) Training Staff : 5 people (professor, Researcher) Remote Centre Resources 1 HP9000 Station Test Software : Agilent SmarTest First I have to situate the problem of education in the field of IC Test And the first think I have to do is to present the state-of-the-art in IC manufacturing Here is the photograph of a Bull Microprocessor which may be considered as a representative Integated Circuit of nowaday manufacturing This IC contains about 7 millions of transistors Implemented on a 2x2 cm2 silicon chip With 428 I/O pins Now what are the problems we have to face when testing such a circuit 23.03.2003 Testmethoden in der Ausbildung

Remote Access to Test Facilities x Remote center CRTC, Montpellier T R C Workstation 1 Test Station Workstation 2 Local HP9000 Workstation 3 Server HP9000 In this context we have to educate electronics engineers to prepare them to this new challenge of managing in parallel the design and the test of nowaday IC's Also, due to the new requirements for IC testing and the very rapid evolution of industrial testers (the so-called ATE, for Automatic Test Equipment) We have to educate in-place engineers who have to face novel test techniques and develop test programs on the generation of mixed-signal Testers ATE Workstation 10 HP83000 F330t 23.03.2003 Testmethoden in der Ausbildung

Digital Test Training (1) Part 1 (one Week): Basics of ATE Programming Preparing the Tests Test Execution and Results Analysis Avanced Test Concepts Test Resource Optimization Automating the Test Program Shmoo Plot 23.03.2003 Testmethoden in der Ausbildung Softscope Mode

Digital Test Training (2) Part 2 (one week): Advanced ATE Programming Timing Optimisation Equation-Based Test Translating Test Programs Advanced Testflow Programming Multi-Site Testing Softscope Mode 23.03.2003 Testmethoden in der Ausbildung Softscope Mode

Testmethoden in der Ausbildung Project Schedule Training implementation UPC (Barcelona) Digital Test Training for trainers (CRTC) Training implementation Politec. (Torino) Training implementation UST (Stuttgart) Training implementation IJS (Ljubljana) Specialized Test (Mixed, Mem.) Training for trainers (CRTC) Mixed-Signal Test Training implementation Sep. 2000 Sep. 2001 Sep. 2002 23.03.2003 Testmethoden in der Ausbildung

Mixed Signal Test Training (1) Basics Principle of the DSP-based Testing Sampling and Synchronization Techniques Histogram-based Test Technique Fourier Analysis Characterization Parameters to be Measured What is the motivation of this work ? In 1997, the French Universities involved in mE education, had to answer the following question: “ How to Meet the Requirements of Microelectronics Industry for Engineers having a double Design & Test Competence ? ” And this was the starting point of the educational experience I plan to describe in this presentation. 23.03.2003 Testmethoden in der Ausbildung 2 2

Mixed Signal Test Training (2) Labs Pin Configuration Level/Timing Setups Mixed-signal File Setup ADC Linearity Test: Gain, Offset, DNL, INL ADC Distortion: THD, SND, SNR Code Count H(i) Code i ADC Test: Sinusoidal Histogram What is the motivation of this work ? In 1997, the French Universities involved in mE education, had to answer the following question: “ How to Meet the Requirements of Microelectronics Industry for Engineers having a double Design & Test Competence ? ” And this was the starting point of the educational experience I plan to describe in this presentation. 23.03.2003 Testmethoden in der Ausbildung 2 2

University/Industry Partnership Tester Company Contribution Pedagogical Competence Research Environment Rooms Consumables . . . Technical Expertise Technical Assistance Hardware : Testers Software . . . Benefits Up-to-Date and Performing ATE 100 trainees/year on specific hardware 23.03.2003 Testmethoden in der Ausbildung