Introduction Course Overview and Basic understanding of Computer Architecture

Assistant Professor Dept. of Computer Science and Engineering Jahangirnager University, Savar, Dhaka Bangladesh Instructor: Abu Sayed Md. Mostafizur Rahaman Teaching Assistant: Rezaur Rahman (Reza) 4 th year 2 nd year student (Appeared) Dept. of Computer Science Engineering Jahangirnagar University, Savar, Dhaka Bangladesh

3 Seat Plan during this course Door

4 Schedule may subject to change  From 23 May, 2011 to 19 September, 2011  Every week (excluding holydays)  Monday  11:00 -13:00 (2 classes)  Wednesday  10: :10 (2 classes) Schedule

5 Lecture Materials  Contains  News and schedule update  Lecture slides  Exercises (at least 5)  Assignments  Additional materials for further readings Computer Architecture

6 References  D.A. Patterson and J.L. Hennessy, Computer Architecture and Design: The Hardware/Software Interface, 4 th edition, Elsevier/Morgan Kauffman.  3 rd edition OK if 4 th edition not available.  Mostafa ABD-Al-Barr & Hesham El-Rewini “Fundamentals of computer organization and architecture” Willy press.  J. Hennessy and D. Patterson, “Computer Architecture: A Quantitative Approach” (3rd Edition), Morgan Kaufmann Publishers, ISBN Computer Architecture

7 Grading Policy  Attendance= 10 %  Assignments= 05 %  Exercises test = 05 %  Instant exams  Class Test (Best of three) = 20 % ====================================== = 40 %  Final Examination= 60 % ====================================== = 100 % Computer Architecture

8 Class Test Schedule Wednesday July 13, 2011 Monday August 08, 2011 Monday August 29, 2011 Monday September 19, 2011 **Schedule may subject to change Computer Architecture

9 Course Overview  Introduction: Instruction codes, formats, cycle, timing etc; Addressing modes; Types of instruction; RISC characteristics; CISC characteristics and Yields.  Chapter 1 & 2 from first reference book (3 lectures)  Computer Arithmetic: Different types of data representation; Addition and subtraction; Multiplication algorithms; Division algorithms.  Chapter 3 from 1 st reference book (3 lectures)  Fundamentals of parallel processing: Parallel processing; Pipelining; Vector processing; Multiprocessors; Array processor, Bit-slice processor Interconnection structures.  From 1 st and 3 rd reference books (4 lectures)  Memory Organization: Main memory; Auxiliary memory; Associative memory; Cache memory; Virtual memory; Memory management requirements and hardware.  Chapter 5 from 1 st reference book (2 lectures)  Parallel Computer Architecture(1 lecture)  Distributed Memory Architecture(1 lecture)  Input-Output Organization: Input-Output Interfaces; Data transfer, Interrupts; Direct Memory Access (DMA); Input-output channel.  Chapter 6 from first reference book (1 lecture) Computer Architecture

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11 What is Computer Architecture? Easy Answer Computer Architecture = Instruction Set Architecture + Machine Organization

12 The Instruction Set: a Critical Interface instruction set software hardware

13 Instruction Set Architecture  A very important abstraction:  interface between hardware and low-level software  standardizes instructions, machine language bit patterns, etc.  advantage: allows different implementations of the same architecture  disadvantage: sometimes prevents adding new innovations  Modern instruction set architectures:  80x86/Pentium/K6, PowerPC, DEC Alpha, MIPS, SPARC, HP

14 I/O systemInstars. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Datapath & Control Layout What is Computer Architecture? Better (More Detailed) Answer

15 Classic Components of a Computer  Input (mouse, keyboard, …)  Output (display, printer, …)  Memory  main (DRAM), cache (SRAM)  secondary (disk, CD, DVD, …)  Datapath  Control Input Processor Control Datapath Output Memory Processor (CPU)

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17 Features and benefits  Intel® Core™2 Duo processor  With an you will get performance-rich technologies, including up to 6MB of shared L2 cache, up to 1333 MHz Front Side Bus, plus these additional Intel® technologies built in:  Intel® multi-core processing  Provides greater multitasking performance by combining two independent processor cores in one physical package¹  Intel® Wide Dynamic Execution  Improves execution time and energy efficiency with more instructions per clock cycle  Intel® Intelligent Power Capability  Enables smarter, more energy-efficient performance  Intel® Smart Memory Access  Improves system performance by optimizing the use of the available data bandwidth  Intel® Advanced Smart Cache  Enables higher performance and more efficient cache subsystem by optimizing for multi-core processors  Intel® Advanced Digital Media Boost accelerates  A broad range of applications including video, speech and image, photo processing, encryption, financial, engineering, and scientific applications Computer Architecture

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