1. (1) ECE 3056: Architecture, Concurrency and Energy in Computation Lecture Notes by MKP and Sudhakar Yalamanchili Sudhakar Yalamanchili (Some small modifications by John Copeland, 2014) School of Electrical and Computer Engineering Georgia Institute of Technology

2. (2) Course Objectives Basic concepts of microprocessor architecture  Instruction Set Architecture (built on ECE 2020 and 2035 concepts)  The Core: ALU, datapath, & control implementation  Multiple Cores: synchronization  Memory hierarchy: cache, virtual memory, disk  Input/output systems  Basic Concurrency Support oMulticore processors oModels of parallel computation  Sources of Energy and Power dissipation oMicroarchitecture level models of energy and power Image from http://blog.mytechhelp.com/laptop-repair/the-ivy-bridge/

3. (3) Course Objectives Understand how computing systems work  Fundamental architectural concepts and challenges  Understanding performance: time, space, and energy Acquire knowledge to optimize systems  As a designer  As a user  As a researcher Assignments  Build simple processor models and apply several hardware optimizations  Build and simulate cache models  Basic support for parallelism  Evaluate energy consumption

4. (4) Where Does the Computing Go? From nytimes.com Computer Engineering Inside eecs.berkely.edu Wireless sensor node Google Data Center AMD Trinity APU

5. (5) What You Will Learn How programs are translated into the machine language  And how the hardware executes them The hardware/software interface What determines program performance  And how it can be improved How hardware designers improve performance What is parallel processing? Where does the energy go?

6. (6) Course Information Web page: http://users.ece.gatech.edu/~copeland/jac/305 6/ And T-Square  Will be constantly updated, so check it regularly Prerequisite: ECE2031, ECE 2035 or 3035 Textbook  Patterson and Hennessey  Patterson and Hennessey, Computer Organization & Design: The Hardware/Software Interface (4 th edition, revised printing), Morgan Kaufmann, 2012. ISBN 978-0-12-374750-1

7. (7) Grading Policy Homework Assignments: 30%  Individual work, no collaboration  No late assignments will be accepted  You must make a passing grade on the assignments to pass the course Exams  2 in-class exams: 40% (20% each, dates TBD)  Final: 30%: December 13 th, 2013, 2:50 pm – 5:40 pm Teaching Assistant: TBD

8. (8) Where Are We? High-level language  Level of abstraction closer to problem domain  Provides for productivity and portability Assembly language  Textual representation of instructions Hardware representation  Binary digits (bits)  Encoded instructions and data ECE 2035 ECE 3056

9. (9) Course Layout  Instruction set architecture  ALU Implementation  Basic Datapath  Pipelined Datapath  Chapter 2, 3, 4, Appendix B, C, D  Cache design  Memory Hierarchy  Virtual Memory System  Chapter 5  Storage Technologies  I/O Systems  Chapter 6  Parallelism & Concurrency  Data, Thread, and Instruction Level Parallelism  Chapter 7, Appendix A Intel Ivy Bridge