© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el al

© Digital Integrated Circuits 2nd Sequential Circuits Other Latches/Registers: TSPC Negative latch Positive latch The main advantage is the use of single clock, but 12 transistors for the register. Also, output node might be floating (dynamic storage). It needs either a static inverter or to be made pseudo-static.

© Digital Integrated Circuits 2nd Sequential Circuits Embedding Logic in true single phase clock AND latch: implements AND + latch Example: logic inside the latch The setup time of the embedding TSPC is smaller compared to the conventional approach, resulting in a smaller clock period, thus improves the system performance. This approach is extensively used in EV4 DEC Alpha and other processors

© Digital Integrated Circuits 2nd Sequential Circuits Simplified TSPC: split output Negative latch Positive latch Advantage: reduced complexity, reduced clock load Disadvantage: not all voltage nodes have full logic swing, e.g., node A for positive latch is V DD -V T when In=0, which results in a reduced drive for the following NMOS. CLKIn V DD V In Out CLK V DD V Out A A

© Digital Integrated Circuits 2nd Sequential Circuits A specialized TSPC Register When CLK=0, X=D, second inverter is in precharge and Y=1. Third inverter is in hold mode. On rising edge of CLK, second inverter evaluates X and third inverter is on and passes Y to Q Hold time: PD time: Setup: 1 inv 3 inv 1 inv X can make only 1- >0 change

© Digital Integrated Circuits 2nd Sequential Circuits An Alternative Approach to register: Pulse-Triggered Latches  Up to now, we have been constructing registers using master-slave configuration.  A fundamentally different approach is to use pulse signals, which is to construct a short pulse around the rising/falling edge of the clock. The pulse acts as the clock input to the latch, sampling the input only in a short window time.  Race condition can be avoided by keeping the opening time of the latch very small.

© Digital Integrated Circuits 2nd Sequential Circuits Pulse-Triggered Latches Master-Slave registers D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered register cell: More used in AMD processors

© Digital Integrated Circuits 2nd Sequential Circuits Pulsed Latches

© Digital Integrated Circuits 2nd Sequential Circuits Pulsed Latches  When CLK=0, node X is charged up to V DD (transistor M N is off now), CLKG=0  When CLK=1, there is a short period of time when both inputs to the AND gate are high, causing CLKG=1. So, there is initial delay between the rising edge of the clock and that of the glitch pulse signal.  When CLKG=1, M N is activated, pulling X to low and eventually CLKG=0. The delay time is the M N delay, AND and two Inverter gates delay, which also determines the pulse width.

© Digital Integrated Circuits 2nd Sequential Circuits Pulsed Latches  Setup time=0, hold time=length of the pulse, propagation delay=two inverter gate delays.  Advantage of the approach is reduced clock load and smaller number of transistors (pulse generation circuitry can be amortized over multiple registers).  Disadvantage is a substantial verification effort (need to simulate all corners to ensure the clock pulse always reliable).

© Digital Integrated Circuits 2nd Sequential Circuits Another Pulsed Latch Hybrid Latch – Flip-flop (HLFF) used in AMD K-6 and K-7 V DD

© Digital Integrated Circuits 2nd Sequential Circuits Another Pulsed Latch  When CLK=0, P1 on, X precharged to 1, Q is decoupled from X and is in hold mode.  On rising edge, M3 and M6 are on and M1/M4 are on for a short period determined by the delay of three inverters. Now, D is sampled by the latch.  Once CLKD goes to low, X is decoupled from D and is either held or precharged to 1 through P2. Overlapping clock pairs CLKD CLK

© Digital Integrated Circuits 2nd Sequential Circuits Hybrid Latch-FF Timing

© Digital Integrated Circuits 2nd Sequential Circuits Pipelining Reference data path Pipelined data path Pipelining is a popular design technique used to accelerate the operation of datapath in microprocessor. It improves resource utilization and increase the functional throughput. Simplifying the analysis, assume each logic module in the reference datapath has equal delay, then each is active for only one-third of the clock period.

© Digital Integrated Circuits 2nd Sequential Circuits Pipelining Reference Pipelined

© Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Pipeline Computed F sampled onto C2 Computed G sampled onto C3 Disadvantage: Potential race condition with clock overlap. (e.g., if input sampled onto C1 propagates to C2 before CLK goes to low) E Operation of the pipeline: When CLK high, E/G writing C1/C3, while C2/C4 hold When CLK low, F/H writing C2/C4, while C1/C3 hold H

© Digital Integrated Circuits 2nd Sequential Circuits Non-Bistable Sequential Circuits─ Schmitt Trigger VTC with hysteresis Fast response time Employs positive feedback

© Digital Integrated Circuits 2nd Sequential Circuits Noise Suppression using Schmitt Trigger

© Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger Moves switching threshold of the first inverter Switching threshold of an inverter is determined by the k n /k p ratio of NMOS/PMOS. Increasing the ratio raises V m, while decreasing the ratio lowers V m. If V in =0 so that V out =0, M4 on, M3 off (M4,M2 together with M1). When it switch, M4 off, M3 on, this speeds up the transition. Similarly with Vi n =1, V out =1.

© Digital Integrated Circuits 2nd Sequential Circuits Schmitt Trigger Simulated VTC 2.5 V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the PMOS deviceM 4. The width isk* 0.5 m. m k = 2 k = 3 k = 4 k = 1 V in (V)

© Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger (2) In=0, Out=1, M5 on so that when In changes from 0 to 1, it has to be larger to discharge M5 (through V DD to M1). On the other hand, once Out switches, M6 on, so positive feedback to allow fast transition (M6 diverts current to GND so that M3, M4 charges less to Out).

© Digital Integrated Circuits 2nd Sequential Circuits Multivibrator Circuits

© Digital Integrated Circuits 2nd Sequential Circuits Transition-Triggered Monostable

© Digital Integrated Circuits 2nd Sequential Circuits Astable Multivibrators (Oscillators) 012N-1 Ring Oscillator simulated response of 5-stage oscillator

© Digital Integrated Circuits 2nd Sequential Circuits PLL Block Diagram  PLL is an analog circuit, which is sensitive to all sources of noise (it might need to be guarded by careful layout).  When stable, the system clock is N times the reference clock frequency and ideally 0 skew from the reference clock