1 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Design a clock synchronous sequential circuit with two inputs A, B and a single output Z that is 1 if: –A had the same value at each of the two previous clock ticks, or –B has been 1 since the last time that the first condition was true. –Otherwise, output should be 0. State Assignment Example

2 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 State definitions: –INIT: initial state –A0: A had 10 but not 00 on the previous clock ticks. –A1: A had 01 but not 11 on the previous clock ticks. –OK0: A had 00, or when OK B=1 and last A=0 –OK1: A had 11, or when OK B=1 and last A=1 State Assignment Example (cont.) A: B: Z:

3 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 How to choose the best state assignment? Formal way: try all assignments! –To much work, not practical. Guidelines for reasonable state assignments: –Choose an initial state into which the machine can easily be forced at reset (00…0 or 11…1). –Minimize the number of state variables that change on each transition. –Maximize the number of state variables that don’t change in a group of related states. –Exploit symmetries in the problem specifications. –Don’t limit the choice of coded states to the first m n-bit integers. –Decompose the set of state variables into individual bits or fields, where each bit or field has a well-defined meaning wrt the input effects or output behavior. –Consider using more than the minimum number of state variables to make, a decomposed assignment, possible.

4 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Ex: Decomposed State Assignment StateQ1Q2Q3Q1Q2Q3 INIT000 A0100 A1101 OK0110 OK1111 Easy to force reset state When Q 1 =1 Q 2 indicates an OK state Q 3 indicates the previous value of A

5 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Ex: One-hot State Assignment StateQ 1 —Q 5 Q 1 —Q 4 (almost one-hot) INIT A A OK OK One bit to each state Simple structure Requires more than minimum number of FFs.

6 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Note on unused states Minimal Risk: –Consider getting one of the unused (or illegal) states (can be hardware failure, design error, etc). –Identify unused states, create next-state transitions to initial, idle or a safe state. Minimal Cost: –Assumes the machine never enters to the unused states. –In the next-state table unused states can be marked as don’t cares. –Simplifies excitation logic, but may create problems.

7 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 State Minimization Should minimize the cost of the final sequential clocked circuit (scct) either by –Reducing the number of gates, or –Reducing the number of FFs One possible way for this minimization is –Elimination of equivalent states. Equivalent states: –If it is impossible to distinguish them by observing the current and future outputs of the machine.

8 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 E  G F  D Present State Next State X=0 X=1 Output X=0 X=1 AAB00 BCD00 CAD00 DEF01 EAF01 FGF01 GAF01 Example on equivalent states: Present State Next State X=0 X=1 Output X=0 X=1 AAB00 BCD00 CAD00 DED01 EAD01

9 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Other Flip-Flop Types J-K and T flip-flops –Behavior –Implementation Basic descriptors for understanding and using different flip-flop types –Characteristic tables –Characteristic equations –Excitation tables For actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops

10 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 J-K Flip-flop Behavior –Same as S-R flip-flop with J analogous to S and K analogous to R –Except that J = K = 1 is allowed, and –For J = K = 1, the flip-flop changes to the opposite state –As a master-slave, has same “1s catching” behavior as S-R flip- flop –If the master changes to the wrong state, that state will be passed to the slave E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle

11 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 J-K Flip-flop (continued) Implementation –To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop  Symbol D C K J J C K

12 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 T Flip-flop Behavior –Has a single input T For T = 0, no change to state For T = 1, changes to opposite state Same as a J-K flip-flop with J = K = T As a master-slave, has same “1s catching” behavior as J-K flip-flop Cannot be initialized to a known state using the T input –Reset (asynchronous or synchronous) essential

13 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 T Flip-flop (continued) Implementation –To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop  Symbol C D T T C

14 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Basic Flip-Flop Descriptors Used in analysis –Characteristic table - defines the next state of the flip- flop in terms of flip-flop inputs and current state –Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state Used in design –Excitation table - defines the flip-flop input variable values as function of the current state and next state

15 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 D Flip-Flop Descriptors Characteristic Table Characteristic Equation Q(t+1) = D Excitation Table D 0 1 Operation Reset Set 0 1 Q(t1) + Q(t+1) D Operation Reset Set

16 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 T Flip-Flop Descriptors Characteristic Table Characteristic Equation Q(t+1) = T  Q Excitation Table No change Complement Operation 0 1 TQ(t1) Q(t) Q(t) + Q(t + 1) Q(t) 1 0 T No change Complement Operation Q(t)

17 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 S-R Flip-Flop Descriptors Characteristic Table Characteristic Equation Q(t+1) = S + R Q, S. R = 0 Excitation Table OperationS R No change Reset Set Undefined 0 1 ? Q(t+1) Q(t) Operation No change Set Reset No change S X Q(t+ 1) Q(t) R X 0 1 0

18 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 J-K Flip-Flop Descriptors Characteristic Table Characteristic Equation Q(t+1) = J Q + K Q Excitation Table No change Set Reset Complement OperationJ K 0 1 Q(t +1) Q(t) Q(t) Q(t + 1) Q(t) Operation X X 0 1 K 0 1 X X J No change Set Reset No Change

19 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Flip-flop Behavior Example Use the characteristic tables to find the output waveforms for the flip- flops shown: T C Clock D,T QDQD QTQT D C

20 KU College of Engineering Elec 204: Digital Systems Design Lecture 17 Flip-Flop Behavior Example (continued) Use the characteristic tables to find the output waveforms for the flip- flops shown: J C K S C R Clock S,J Q SR Q JK R,K ?