1. Chapter 5 – Sequential Circuits
Logic and Computer Design Fundamentals
Chapter 5 – Sequential Circuits
Part 2 – Sequential Circuit Design
Haifeng Liu
2014 Fall
College of Computer Science and Technology, Zhejiang University

2. Overview Part 1 - Storage Elements and Analysis
Introduction to sequential circuits
Types of sequential circuits
Storage elements
Latches
Flip-flops
Sequential circuit analysis
State tables
State diagrams
Circuit and System Timing
Part 2 - Sequential Circuit Design
Specification
State Assignment
Designing

3. The Design Procedure Specification
Formulation - Obtain a state diagram or state table
State Assignment - Assign binary codes to the states
Flip-Flop Input Equation Determination - Select flip-flop types and derive flip-flop equations from next state entries in the table
Output Equation Determination - Derive output equations from output entries in the table
Optimization - Optimize the equations
Technology Mapping - Find circuit from equations and map to flip-flops and gate technology
Verification - Verify correctness of final design

4. Specification Components of Specification Verbal description
Mathematical description
Hardware description language*
Tabular description*
Equation description*
Diagram describing operation (not just structure)*

5. Formulation: Finding a State Diagram
A state is an abstraction of the history of the past applied inputs to the circuit (including power-up reset or system reset).
The interpretation of “past inputs” is tied to the synchronous operation of the circuit. e.g., an input value (other than an asynchronous reset) is measured only during the setup-hold time interval for an edge-triggered flip-flop.
Examples:
State A represents the fact that a 1 input has occurred among the past inputs.
State B represents the fact that a 0 followed by a 1 have occurred as the most recent past two inputs.

6. Formulation: Finding a State Diagram
In specifying a circuit, we use states to remember meaningful properties of past input sequences that are essential to predicting future output values.
A sequence recognizer is a sequential circuit that produces a distinct output value whenever a prescribed pattern of input symbols occur in sequence, i.e, recognizes an input sequence occurrence.
We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram.
Next, the state diagram, will be converted to a state table from which the circuit will be designed.

7. Sequence Recognizer Procedure
To develop a sequence recognizer state diagram:
Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically “reset” state).
Add a state that recognizes that the first symbol has occurred.
Add states that recognize each successive symbol occurring.
The final state represents the input sequence (possibly less the final input value) occurrence.
Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred.
Add other arcs on non-sequence inputs which transition to states that represent the input subsequence that has occurred.
The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since “reset.”.

8. Sequence Recognizer Example
Example: Recognize the sequence 1101
Note that the sequence contains 1101 and "11" is a proper sub-sequence of the sequence.
Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol.
Also, the sequence contains 1101 as both an initial subsequence and a final subsequence with some overlap, i. e., or
And, the 1 in the middle, , is in both subsequences.
The sequence 1101 must be recognized each time it occurs in the input sequence.

9. Example: Recognize 1101
Define states for the sequence to be recognized:
assuming it starts with first symbol,
continues through each symbol in the sequence to be recognized, and
uses output 1 to mean the full sequence has occurred,
with output 0 otherwise.
Starting in the initial state (Arbitrarily named "A"):
Add a state that recognizes the first "1"
State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "0" means that the full recognized sequence has not yet occurred. B
1/0 A
序列长度为4，至少4个状态。

10. Example: Recognize 1101 (continued)
After one more 1, we have:
C is the state obtained when the input sequence has two "1"s.
Finally, after 110 and a 1, we have:
Transition arcs are used to denote the output function (Mealy Model)
Output 1 on the arc from D means the sequence has been recognized
To what state should the arc from state D go? Remember: ?
Note that D is the last state but the output 1 occurs for the input applied in D. This is the case when a Mealy model is assumed. A B
1/0 C
1/0 A B
1/0 C
0/0 D
1/1

11. Example: Recognize 1101 (continued)B
1/0 C
0/0 D
1/1
Clearly the final 1 in the recognized sequence is a sub-sequence of It follows a 0 which is not a sub-sequence of Thus it should represent the same state reached from the initial state after a first 1 is observed. We obtain:
1/1 D A B
1/0 C
0/0

12. Example: Recognize 1101 (continued)
1/1 A B
1/0 C D
0/0
The state have the following abstract meanings:
A: No proper sub-sequence of the sequence has occurred.
B: The sub-sequence 1 has occurred.
C: The sub-sequence 11 has occurred.
D: The sub-sequence 110 has occurred.
The 1/1 on the arc from D to B means that the last 1 has occurred and thus, the sequence is recognized.

13. Example: Recognize 1101 (continued)
The other arcs are added to each state for inputs not yet listed. Which arcs are missing?
Answer:
"0" arc from A "0" arc from B "1" arc from C "0" arc from D.
1/0
1/0
0/0 A B C D
1/1

14. Example: Recognize 1101 (continued)
State transition arcs must represent the fact that an input subsequence has occurred. Thus we get:
Note that the 1 arc from state C to state C implies that State C means two or more 1's have occurred.
0/0
1/0
1/1 A B
1/0 D
0/0 C
0/0
0/0

15. Formulation: Find State Table
From the State Diagram, we can fill in the State Table.
There are 4 states, one input, and one output We will choose the form with four rows, one for each current state.
From State A, the 0 and input transitions have been filled in along with the outputs.
1/0
0/0
1/1 A B C D
0/0 A
1/0 B
Present State
Next State
x=0 x=1
Output A B C D

16. Formulation: Find State Table
From the state diagram, we complete the state table.
What would the state diagram and state table look like for the Moore model?
1/0
0/0
1/1 A B C D
Present State
Next State
Output
x=0 x=1
x=0 x=1 A
A B B
A C C
D C D
A B

17. Example: Moore Model for Sequence 1101
For the Moore Model, outputs are associated with states.
We need to add a state "E" with output value 1 for the final 1 in the recognized input sequence.
This new state E, though similar to B, would generate an output of 1 and thus be different from B.
The Moore model for a sequence recognizer usually has more states than the Mealy model.

18. Example: Moore Model (continued)
We mark outputs on states for Moore model
Arcs now show only state transitions
Add a new state E to produce the output 1
Note that the new state, E produces the same behavior in the future as state B. But it gives a different output at the present time. Thus these states do represent a different abstraction of the input history.
A/0
B/0
C/0
D/0
E/1 1

19. Example: Moore Model (continued)
The state table is shown below
A/0
B/0
C/0
D/0
E/1 1
Present State
Next State
x=0 x=1
Output y A B C D E 1
输出只和状态有关，和输入无关了。

20. State Assignment Each of the m states must be assigned a unique code
Minimum number of bits required is n such that n ≥ log2 m where x is the smallest integer ≥ x
There are useful state assignments that use more than the minimum number of bits
There are 2n - m unused states
多余的状态：注意这些状态实际是存在的，万一系统进入到这些状态，能否自恢复。
Chapter 5 - Part

21. State Assignment – Example 1
Present State
Next State
x=0 x=1
Output
x=0 x=1 A B 1
How may assignments of codes with a minimum number of bits?
Two: A = 0, B = 1 or A = 1, B = 0
Does it make a difference?
Only in variable inversion, so small, if any.
4个状态，2个变量，有24种分配方案

22. State Assignment – Example 2
Present State
Next State
x=0 x=1
Output
x=0 x=1 A
A B B
A C C
D C D
How may assignments of codes with a minimum number of bits?
4  3  2  1 = 24
Does code assignment make a difference in cost?

23. State Assignment – Example 2 (continued)
Assignment 1: A = 0 0, B = 0 1, C = 1 0, D = 1 1
The resulting coded state table:
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 0
1 1 1
输入：现态(y1,y2) +输入x
输出：次态+输出z

24. Find Flip-Flop Input and Output Equations: Example 2 - Assignment 1
Assume D flip-flops
Interchange the bottom two rows of the state table, to obtain K-maps for D1, D2, and Z: D1 D2 Z Y2 Y1 X 1 Y2 Y1 X 1 Y2 Y1 X 1

25. Optimization: Example 2: Assignment 1
Performing two-level optimization:
D1 = Y1Y2 + XY1Y2 D2 = XY1Y2 + XY1Y2 + XY1Y2 Z = XY1Y Gate Input Cost = 22 D1 D2 Z Y2 Y1 X 1 Y2 Y1 X 1 Y2 Y1 X 1
D1=7
D2 =12
D3=3

26. State Assignment – Example 2 (continued)
Assignment 2: A = 0 0, B = 0 1, C = 1 1, D = 1 0
The resulting coded state table:
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 1
1 0 1

27. Find Flip-Flop Input and Output Equations: Example 2 - Assignment 2
Assume D flip-flops
Obtain K-maps for D1, D2, and Z: D1 D2 Z Y2 Y1 X 1 Y2 Y1 X 1 Y2 Y1 X 1

28. Optimization: Example 2: Assignment 2
Performing two-level optimization:
D1 = Y1Y2 + XY Gate Input Cost = 9 D2 = X Select this state assignment for Z = XY1Y2 completion of the design D1 D2 Z Y2 Y1 X 1 Y2 Y1 X 1 Y2 Y1 X 1
D1：6
D2：0
D3：3

29. Map Technology Library: Initial Circuit:
D Flip-flops with Reset (not inverted)
NAND gates with up to 4 inputs and inverters
Initial Circuit:
Clock D C R Y2 Z Y1 X
Reset

30. Mapped Circuit - Final Result
Clock D C R Y2 Z Y1 X
Reset

31. State Assignment
Generally different assignments will result in different output functions, excitation functions, and the complexity of circuit varies as well. The tasks of state assignment are:
Determine the length of code
Find the best state assignment or close to the best
Finding a best assignment can be extremely hard when n is large enough. And the performance of the state assignment also depends on the type of triggers. In practice, state assignment is processed in an engineering way, where the following rules are applied.

32. Basic Rules For State Assignment
The states which have the same next states with the same inputs should be assigned adjacent binary codes
The next states of a present state with adjacent inputs should be assigned adjacent binary codes
The states with the same output should be assigned adjacent binary codes
Initial state or the most frequently used state should be assigned code 0
4条原则，优先级由大到小

33. Basic Rules For State Assignment (Continued)
The first rule is the most important, should be considered first
According to the former three rules, state pairs with more present times should be assigned adjacent codes with high priority

34. Example: State Assignment
Rule 1: A-B, A-C
Rule 2: C-D, A-C, B-D, A-B
Rule 3: A-B, A-C, B-C
Rule 4: A = 0
Next State/ Output
Present State
X=0
X=1 A B C D
C/0
B/0
A/1
D/0
A/0
B/1

35. Example: State Assignment (Continued)
n=2, since 2 triggers is enough to represent 4 states
Determine the assignment
Rule 1: A-B, A-C
Rule 2: C-D, A-C, B-D, A-B
Rule 3: A-B, A-C, B-C
Rule 4: A = 0

36. Example: State Assignment (Continued)Y1 Y2 1 A B C D
Rule 1: A-B, A-C
Rule 2: C-D, A-C, B-D, A-B
Rule 3: A-B, A-C, B-C
Rule 4: A = 0 Y2 Y1 A B 1 C D

37. Example: State Assignment (Continued)
Final State Table
Sometimes, the assignment that fit the requirement is not unique. And any of them is suitable.
Present State
y2 y1
y2(t+1)y1(t+1) / Output
X=0
X=1
0 0
10/0
11/0
0 1
00/0
1 1
00/1
01/1
1 0
01/0
Present State
Next State/ Output
X=0
X=1 A
C/0
D/0 B
A/0 C
B/0 D
A/1
B/1
根据分配原则得到的分配方案不一定唯一，例如B和C对调一下，也是可以的。

38. Sequential Design: Example 3
Design a sequential modulo 3 accumulator for 2-bit operands
Definitions:
Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n
Example: modulo 3 = remainder of 4/3 = 1
Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.
Stored sum: (Y1,Y0), Input: (X1,X0), Output: (Z1,Z0)
累加器的值，就是和的值，也就是输出的值，也是状态的值。

39. Example 3 (continued) Complete the state diagram: 00 Reset A/00 01
B/01
Add arc labeled 10 from state A to state C
Add arc labeled 00 from state B to state B
Add arc labeled 01 from state B to state C
Add arc labeled 10 from state B to state A
Add arc labeled 00 from state C to state C
Add arc labeled 01 from state C to state A
Add arc labeled 10 from state C to state B

40. Example 3 (continued) Complete the state diagram: 00 Reset A/00 01 10
B/01
Add arc labeled 10 from state A to state C
Add arc labeled 00 from state B to state B
Add arc labeled 01 from state B to state C
Add arc labeled 10 from state B to state A
Add arc labeled 00 from state C to state C
Add arc labeled 01 from state C to state A
Add arc labeled 10 from state C to state B 00 00 10

41. Example 3 (continued) Complete the state table 00 01 11 10 Z1Z0 A (00)
State Assignment: (Y1,Y0) = (Z1,Z0)
Codes are in gray code order to ease use of K-maps in the next step
X1X0
Y1Y0 00 01 11 10
Z1Z0
Y1(t+1), Y0(t+1)
A (00) X
B (01)
- (11)
C (10)
Add entry 01 in (00),(01)
Add entry 10 in (00)(10) Add entry 01 in (01)(00)
Add entry 10 in (01)(01)
Add entry 00 in (01)(10)
Add entry 10 in (10)(00)
Add entry 00 in (10)(01)
Add entry 01 in (10)(10)

42. Example 3 (continued) Complete the state table 00 01 11 10 Z1Z0 A (00)
State Assignment: (Y1,Y0) = (Z1,Z0)
Codes are in gray code order to ease use of K-maps in the next step
X1X0
Y1Y0 00 01 11 10
Z1Z0
Y1(t+1), Y0(t+1)
A (00) X
B (01)
- (11)
C (10)
Add entry 01 in (00),(01)
Add entry 10 in (00)(10) Add entry 01 in (01)(00)
Add entry 10 in (01)(01)
Add entry 00 in (01)(10)
Add entry 10 in (10)(00)
Add entry 00 in (10)(01)
Add entry 01 in (10)(10)

43. Example 3 (continued) Y0 Y1 D1 D0 X1 X X0
Find optimized flip-flop input equations for D flip-flops
D1 =
D0 = D1 Y0 Y1 X1 X0 X D0
Entries in locations 0 through 15 for D1 = 0,0,1,X; 0,1,0,X;1,0,0,X; X,X,X,X
Entries in locations 0 through 15 for D0 = 0,1,0,X; 1,0,0,X;0,0,1,X; X,X,X,X
Prime implicants (all essential) are given in the equations below:
D1 = Y1X1’X0’ + Y0X0 + Y1’Y0’X1
D0 = Y0X1’X0’ + Y1X1 + Y1’Y0’X0

44. Example 3 (continued) Y0 Y1 D1 D0 X1 1 1 1 1 X 1 1 X0
Find optimized flip-flop input equations for D flip-flops
D1 = Y1 X1X0 + Y0X0 + Y1Y0X1
D0 = Y0X1X0 + Y1X1 + Y1Y0X0 D1 Y0 Y1 X1 X0 X D0 1 1 1 1 1 1
Entries in locations 0 through 15 for D1 = 0,0,1,X; 0,1,0,X;1,0,0,X; X,X,X,X
Entries in locations 0 through 15 for D0 = 0,1,0,X; 1,0,0,X;0,0,1,X; X,X,X,X
Prime implicants (all essential) are given in the equations below:
D1 = Y1X1’X0’ + Y0X0 + Y1’Y0’X1
D0 = Y0X1’X0’ + Y1X1 + Y1’Y0’X0

45. Circuit - Final Result with AND, OR, NOTX1 D C R Y1 Z1 X0 Y0 D Z0
输出值就是状态值 C R
Reset
Clock

46. Simplification of State Table
Generally, original state table may contain some redundant states, which will increase the cost of the design
Simplification of State Table: Get a minimized state table, which can satisfy the design requirement with least number of states

47. Equivalent States
Complete State Table: All next states and outputs in the state table have certain state and value.
Equivalent States: Assume S1 and S2 are two states in the complete state table, and begin with S1 and S2, if we have exactly same output sequence for any input sequence, S1 and S2 are called equivalent states, denoted (S1, S2). Equivalent states can be merged. Here, “any input sequence” means that the length and structure of the sequence can be arbitrary

48. Discrimination of Equivalent States
Three cases of equivalent states
For the all inputs,
Firstly, Outputs are the same
Next States are the same
Or Next States are interleaved
Or Next States are circulated
And

49. Next States are the sameSl
0/1 Si Sj Sk
1/0
0/1
1/0 X 1 … Si
Sl/1
Sk/0 Sj Qn
Next States are the same

50. Next States are the sameSi Sj Sk
0/0
1/0
1/0
0/0 X 1 … Si
Sk/0
Sj/0 Sj
Si/0 Qn
Next States are the same
or interleaved

51. Next States are interleaved or equivalent (Sk, Sl are equivalent)
0/1 Si Sj
1/0
1/0 X 1 … Si
Sk/1
Sj/0 Sj
Sl/1
Si/0 Qn
Next States are interleaved
or equivalent (Sk, Sl are equivalent)

52. Next States are interleaved or equivalent or circulated
0/1 Sk Sl
0/0 Si Sj Sm
1/0
1/0
1/0 X 1 … Si
Sk/0
Sj/0 Sk
Si/1
Sm/0 Sl
Sj/1 Sj
Sl/0
Si/0 Qn
Next States are interleaved
or equivalent or circulated

53. 1. Simplify by Observation
Example 1:
Next State/ Output
Present State
X=0
X=1 A B C D
A/0
B/0
C/0
D/1

54. 1. Simplify by Observation (Continued)
Outputs of A and B, C and D are the same
The next states of C and D are the same for all the possible inputs combination, so C and D are equivalent
Because B and C are not equivalent, A and B are not equivalent
Max Equivalent Classes are {A}，{B}，{C,D}, labeled as A', B', C'

55. 1. Simplify by Observation (Continued)
Minimized State Table is
Present State
Next State/ Output
X=0
X=1 A' B' C'
A'/0
B'/0
C'/0
C'/1

56. 2. Simplify by Hidden Table
Example 2:
Present State
Next State/ Output
X=0
X=1 A B C D E F G
C/0
F/0
D/0
D/1
C/1
B/1
A/1
G/0
E/0
E/1

57. 2. Simplify by Hidden Table (Continued)X Qn 1 A
C/0
B/1 B
F/0
A/1 C
D/0
G/0 D
D/1
E/0 E
E/1 F G
C/1
Compare orderly to find equivalent states
If states equivalent, mark “√”
If states not equivalent, mark “×”
If need further comparison, label pair of next states A B C D E F G CF AE CF BE √ CD DE

58. 2. Simplify by Hidden Table (Continued)
Correlatively compare to find equivalent states A B C D E F G CF BE AE √ CD DE
CD, DE are not equivalent, so DG are not equivalent
AB→CF
AE→BE→CF
All the states in the cycle are equivalent

59. 2. Simplify by Hidden Table (Continued)
Determine Max Equivalent Classes
Four equivalent pairs (A,B), (A,E), (B,E), (C,F)
Max Equivalent Classes (A,B,E)
Four states (A,B,E), (C,F), (D), (G)
Label the four states as a, b, c, d

60. 2. Simplify by Hidden Table (Continued)
Minimized State Table:
Present State
Next State/ Output
x=0
x=1 a b c d
b/0
c/0
c/1
b/1
a/1
d/0
a/0

61. Example: Simplify the State Table
AD equivalent
BC equivalent A B C D BC AD X Q 1 A
A/0
B/0 B
A/1
C/0 C
D/1 D X Q 1 A
A/0
B/0 B
A/1

62. Other Flip-Flop Types J-K and T flip-flops
Behavior
Implementation
Basic descriptors for understanding and using different flip-flop types
Characteristic tables
Characteristic equations
Excitation tables
特征表 – 状态表，定义触发器的次态与现态和输入的关系
特征方程 – 次态方程，将触发器的次态定义为触发器输入和现态的逻辑函数
激励表 – 输入方程，将触发器的输入定义为现态和次态的函数
JK触发器和T触发器主要是计数用。

63. J-K Flip-flop Behavior
Same as S-R flip-flop with J analogous to S and K analogous to R
Except that J = K = 1 is allowed, and
For J = K = 1, the flip-flop changes to the opposite state
As a master-slave, has same “1s catching” behavior as S-R flip-flop
If the master changes to the wrong state, that state will be passed to the slave
E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle

64. J-K Flip-flop (continued)
Implementation
To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop 符号 J C K D C K J

65. T Flip-flop Behavior Same as a J-K flip-flop with J = K = T
Has a single input T
For T = 0, no change to state
For T = 1, changes to opposite state
Same as a J-K flip-flop with J = K = T
As a master-slave, has same “1s catching” behavior as J-K flip-flop
Cannot be initialized to a known state using the T input
Reset (asynchronous or synchronous) essential

66. T Flip-flop (continued)
Implementation
To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop 符号 T C C D T

67. Basic Flip-Flop Descriptors
Used in analysis
Characteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state
Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state
Used in design
Excitation table - defines the flip-flop input variable values as function of the current state and next state

68. D Flip-Flop Descriptors
Characteristic Table
Characteristic Equation Q(t+1) = D
Excitation Table D 1
Operation
Reset
Set
Q(t 1) +
Q(t
+1) 1 D
Operation
Reset
Set

69. T Flip-Flop Descriptors
Characteristic Table
Characteristic Equation Q(t+1) = T Å Q
Excitation Table T
Q(t + 1)
Operation
No change Q ( t ) 1 Q ( t )
Complement +
Q(t 1) T
Operation Q ( t )
No change Q ( t ) 1
Complement

70. S-R Flip-Flop Descriptors
Characteristic Table
Characteristic Equation Q(t+1) = S + R Q, S.R = 0
Excitation Table S R
Q(t + 1)
Operation Q ( t )
No change 1
Reset 1 1
Set 1 1 ?
Undefined
Operation
No change
Set
Reset S X 1
Q(t+ 1)
Q(t) R

71. J-K Flip-Flop Descriptors
Characteristic Table
Characteristic Equation Q(t+1) = J Q + K Q
Excitation Table 1
No change
Set
Reset
Complement
Operation J K
Q(t + 1) Q ( t )
Q(t)
Q(t + 1) J K
Operation X
No change 1 1 X
Set 1 X 1
Reset 1 1 X
No Change

72. Flip-flop Behavior Example
Use the characteristic tables to find the output waveforms for the flip-flops shown:
Clock
D,T D C QD
边沿触发 T C QT

73. Flip-Flop Behavior Example (continued)
Use the characteristic tables to find the output waveforms for the flip-flops shown:
Clock
S,J
R,K S C R
QSR ?
SR负脉冲末端触发
JK边沿触发 J C K
QJK

74. Sequential Machines Description-1
Mealy Model
Next State: F
Logic Output Z
Input Q
State
Reg c
Present State
Clock
Excitation
Signal
Output
输出逻辑是组合逻辑，输出值随输入变化而立刻发生变化，容易出错。比如硬盘的磁头电机，来一组脉冲就转一定的角度，方向控制信号是输入信号。多次改变方向的时候就容易出现误差。输出和时钟不同步，所以一般就采用moore型。
Next State: F(state, input)
Output: Z(state, input)

75. Sequential Machines Description-2
Moore Model
Next State: F
Logic Output Z
Input
Excitation
Signal Q
State
Reg c
Present State
Clock
Output
Next State: F(state, input)
Output: Z(state)
When designing high-speed circuit, state variable can be used directly by the output pipeline, which means the output and the clock can be synchronized.

76. Sequential Machines Description-3
Structure of State Machine in pipeline---- Mealy Model
Next State F
Output Logic Z
Input
Excitation
Signal Q
State
Reg
clk
Present State
Output
Pipeline
When designing high-speed circuit, the output of state machine and the clock always need to be completely synchronized. One solution is to just use state variable as output signal.

77. Description of State Machine with Verilog
State Machine as follows:
X=1
State1
X=1/Z2=0 Z1=0
Reset=0 /Z2=0 Z1=0
Reset=0 /Z2=0 Z1=0
X=0
idle
Reset=0 /Z2=0 Z1=0
State2
用硬件描述语言怎么样来设计状态机。
我们现在的实验工具是可以直接输入状态图的。但是我们是要学习，所以不希望直接输入状态图。而且调试的时候很麻烦，因为状态机的生成是自动生成，调试的时候很难跟踪这些模块。所以一般都是自己写的状态机作为输入。
State 3
X=1/Z2=1
Reset=0orX=0/Z2=0 Z1=1
X=0
X=1

78. Description of State Machine with Verilog (1) ---- Use Gray Code as State Code
module fsm (Clock, Reset, X, Z2, Z1);
input Clock, Reset, X;
output Z2, Z1;
reg Z2, Z1;
reg [1:0] state ;
parameter Idle = 2’b00, State_1 = 2’b01,
State_2 = 2’b10, State_3 = 2’b11;
Clock)
if (!Reset)
begin
state <= Idle; Z2<=0; Z1<=0;
end
else
case (state)
Idle: begin
if (X) begin
state <= State_1;
Z1<=0; Z2<=0
else state <= Idle;
State_1: begin
if (!X) state <= State_2;
else state <= State_1;
end
State_2: begin
if (X) begin
state <= State_3；
Z2<= 1;
else state <= State_2;
State_3: begin
if (!X) begin
state <=Idle;
Z2<=0; Z1<=1;
else state <= State_3;
endcase
endmodule
Gray码 可靠性比较高。
时钟信号要用这种阻塞型的，表示在时钟上升沿触发，状态才会改变，变量值也才会发生变化。
输出很复杂的时候，会把输出和状态分开来写。

79. Description of State Machine with Verilog (2) ---- Use One-Hot Code as State Code
module fsm (Clock, Reset, X, Z2, Z1);
input Clock, Reset, X;
output Z2, Z1;
reg Z2, Z1;
reg [3:0] state ;
parameter Idle = 4’b1000, State_1 = 4’b0100, State_2 =4’b0010, State_3 =4’b0001;
clock)
if (!Reset)
begin
state <= Idle; Z2<=0; Z1<=0;
end
else
case (state)
Idle: begin
if (X) begin
state <= State_1;
Z1<=0;
else state <= Idle;
State_1: begin
if (!X) state <= State_2;
else state <= State_1;
end
State_2: begin
if (X) begin
state <= State_3；
Z2<= 1;
else state <= State_2;
State_3: begin
if (!X) begin
state <=Idle;
Z2<=0; Z1<=1;
else state <= State_3;
endcase
endmodule
独热码
状态少的时候可以，多的时候触发器太多了，这种编码就不太好了。

80. Description of State Machine with Verilog (3) ---- Use Output Value as State Code
module fsm (Clock, Reset, X, Z2, Z1);
input Clock, Reset, X;
output Z2, Z1;
reg [3:0] state ;
assign Z2= state[3];
// 把状态变量的最高位用作输出Z2
assign Z1= state[0];
// 把状态变量的最低位用作输出Z1
parameter // Z2_S2_S1_Z1
zero = 4'b0000,
Idle = 4'b0001,
State_1 = 4'b0100,
State_2 = 4'b0010,
State_3 = 4'b1000;
Clock)
if (!Reset)
begin
state <= Zero;
end
else
case (state)
Idle, Zero: begin
if (X) begin
state <= State_1;
end
else state <= Zero;
State_1: begin
if (!X) state <= State_2;
else state <= State_1;
State_2: begin if (X) begin
state <= State_3;
else state <= State_2;
State_3: begin if (!X) begin
state <=Idle;
else state <= State_3;
default: state <=Zero;
endcase
endmodule
输出值少，状态多，可以把状态码里的某几位是输出值。
状态机里就不需要对输出进行赋值了。

81. Description of State Machine with Verilog (4) ---- Complicate State Machine with multi-outputs
module fsm (Clock, Reset, X, Z2, Z1);
input Clock, Reset, X;
output Z2, Z1;
reg Z2, Z1;
reg [1:0] state ;
parameter
Idle = 2'b00, State_1 = 2'b01,
State_2 = 2'b10, State_3 = 2'b11;
Clock)
if (!Reset)
state <= Idle;
else
case (state)
Idle: begin if (X) begin
state <= State_1;
end
else state <= Idle;
State_1: begin
if (!X) state <= State_2;
else state <= State_1;
State_2: begin
if (X) state <= State_3;
else state <= State_2;
end
State_3: begin
if (!X) state <=Idle;
else state <= State_3;
default: state <=2'bxx;
endcase
or Reset) //产生输出Z2模块
if (!Reset) Z2=0;
else
if (state == State_3) Z2=1;
else Z2= 0;
or Reset) //产生输出Z1模块
if (!Reset) Z1=0;
if (state == Idle) Z1=1;
else Z1=0;
endmodule
状态变化和输出分开，两个always语句。第一个是状态变换，第二个是输出。也可以每个输出一个always语句。
输出赋值用=（组合电路），不用<=（时序电路），因为在状态变化时需要输出立刻变化。
逻辑电路里有if，一定有else, 要不然没办法综合了，或者给综合成时序电路。

82. Assignments:
5-20; 5-21; 5-24; 5-28; 5-33