FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Global Timing Constraints

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2009 Xilinx, Inc. All Rights Reserved Objectives After completing this module you will be able to…  Apply global timing constraints to a simple synchronous design  Use the Xilinx Constraints Editor to specify global timing constraints

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2009 Xilinx, Inc. All Rights Reserved The Effects of Timing Constraints  With global timing constraints  All timing paths are evaluated  I/O paths are improved (CLBs are place closer to I/O pins)  Without global timing constraints  Logic tends to be grouped to improve internal timing at the expense of I/O timing

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved Timing Constraints Define Your Performance Objectives  Timing constraints define your timing objectives – Over-constraining gets you nothing, but costs extra PAR time – Always use timing constraints, even when your timing objective is modest  Unrealistic timing constraints will cause the tools to stop – Your synthesis tool’s timing report and the Post-Map Static Timing Report contain performance estimates – Both will tell you if your constraints are realistic  After implementing, review the Post-Place & Route Static Timing Report to determine if your objectives were met – If your constraints failed, use the Timing Report to determine the cause

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Path Endpoints  Path Endpoints are… – I/O pads – Synchronous elements FFs, Latches, Rams, DSP slices, SRLs, etc. Flip-FlopsLatches RAMs DSP48  Path Endpoints do NOT include… – LUTs – Nets, or any other asynchronous element

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Creating Timing Constraints Step 1: Create groups of path endpoints Step 2: Specify a timing requirement between the groups  Creating timing constraints is a two step process  Global timing constraints use a default grouping of path endpoints which makes it easy to constrain your design

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved PERIOD Constraint Q FLOP1 DQ FLOP3 D BUFG CLK ADATA OUT2 OUT1 Q FLOP5 D Q FLOP4 D BUS [7..0] CDATA Q FLOP2 D  The PERIOD constraint covers paths between synchronous elements on a single clock domain – In this example, there is one clock signal (CLK) – There are five synchronous elements (all FFs) attach to the clock which means there are five path endpoints, in this case – There are three delay paths constrained between those five FFs

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved PERIOD Constraint  The PERIOD constraint uses the most accurate timing information, so it considers…  Clock skew between the source and destination flip-flops  Synchronous elements clocked on the negative edge  Unequal clock duty cycles  Clock input jitter  The Implementation tools use this information to place and route your design

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Example of the PERIOD Constraint  Assume… – 50-percent duty cycle on CLK – PERIOD constraint of 10 ns – Because FF2 will be clocked on the falling edge of CLK, the path between the two flip-flops will be constrained to 50 percent of 10 ns = 5 ns – The implementation tools will automatically take into account that you are triggering one FF on the rising edge and another on the negative edge BUFG INV CLK FF1 FF2

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Clock Input Jitter  The Xilinx Constraints Editor allows you to enter the input clock jitter  The Implementation tools will then use this information to manage the place and route solution found so the distributed clocks jitter can be tolerated

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved OFFSET IN/OUT Constraints = Combinatorial Logic CLK ADATA OUT2 OUT1 Q FLOP DQ D Q D Q D BUS [7..0] CDATA Q FLOP D BUFG OFFSET INOFFSET OUT  The Offset In constraint covers paths from input pads to synchronous elements  The Offset Out constraint covers paths from synchronous elements to output pads

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved OFFSET IN/OUT Constraints  The Offset In/Out constraints takes the clock delay into account to report an effective input and output delay  OFFSET IN = T_data_In - T_clk_In  OFFSET OUT = T_data_Out + T_clk_Out Out Clk T_data _In T_data _Out T_clk _In OFFSET-OUT OFFSET-IN In T_clk _Out

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved OFFSET Constraints Reporting  Timing constraint reporting is handled by the Timing Analyzer  The Offset In/Out constraints take into account the clock delay and jitter

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Apply Your Knowledge Which paths are constrained by a Period constraint on CLK1? – 1 path is constrained, FF to Latch Which paths are constrained by a Period constraint on CLK2? – No paths are constrained, only 1 synchronous element

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Launching the Constraints Editor  Expand User Constraints in the Processes window  Double-click Create Timing Constraints

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Entering a PERIOD Constraint  PERIOD constraints can be entered by clicking Clock Domains  Constraints can be deleted by right- clicking the constraint  Right-click here and select Create Constraint to make a PERIOD constraint

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved Multiple UCF Files  Select which UCF to edit  Many designers keep their timing constraints in a separate UCF file – User Constraints File (user editable in many text editors) – Some designers like to keep their pin assignments, area constraints, and placement constraints in a separate UCF

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved PERIOD Constraint Options  TIMESPEC name  Specific constraint value – Active clock edge – Duty cycle  Relative to other PERIOD TIMESPEC – Useful for designs with multiple clock signals – Can define both frequency and phase relationships  Input jitter

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Entering OFFSET Constraints  Global OFFSET IN and OFFSET OUT constraints can be made from Inputs or Outputs  Right-click here and select Create Constraint to make an OFFSET constraint

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved Apply Your Knowledge Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? – Assume no clock skew between devices 4 ns 5 ns Upstream Device Downstream Device

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Answer Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz?  Answer: PERIOD = 10 ns, OFFSET IN = 6 ns, and OFFSET OUT = 5 ns 4 ns 5 ns 10 ns 6 ns 5 ns Upstream Device Downstream Device

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Summary  Performance expectations are communicated with timing constraints  The PERIOD constraint covers delay paths between synchronous elements  The OFFSET IN constraint covers delay paths from input pins to synchronous elements  The OFFSET OUT constraint covers delay paths from synchronous elements to output pins  Use the Constraints Editor to create timing constraints

© 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More?  Constraints Guide – Help  Software Manuals Entry strategies (UCF syntax and HDL syntax) Advanced timing constraints  Timing Constraints User Guide – Help  Software Manuals XST synthesis constraints Placement and Area constraints UCF syntax  Xilinx Training – Path Specific Constraints are included with the Designing for Performance course Xilinx tools and architecture courses Basic FPGA architecture, Basic HDL Coding Techniques, and other Free training videos!

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