M. Lozano, E. Cabruja, A. Collado Summary of Bump Bonding Techniques for Pixel Systems Centro Nacional de Microelectrónica Barcelona (Spain)

VERTEX /31 INDEX l Pixel systems l Summary of bump bonding techniques l Technology comparison and forecasts l Testing issues l Thermal issues l Conclusions

VERTEX /31 Pixels systems l Pixel detector chip â Two dimensional diode array â Material: Si, diamond, SiC, GaAs, CdTe, CdZnT l Electronics chip â Built on a separate substrate â Provides: Amplification, data storage, data compression, communication l Pixel detector bonded to electronics

VERTEX /31 Pixel systems l Small pixel size ( µm) l High number of pixels ( ) l Very low leakage current l Low cross talk between pixels l Unaffordable with conventional bonding technologies l Ideally suited for bump bonding flip chip technology l Not commercially available (yet) Many difficulties to be solved

VERTEX /31 Bump bonding flip chip technology l Process steps: â Direct bonding â Rerouting »Detector and/or amplifier chips â Under Bump Metallisation (UBM) â Bumping »On detector or on amplifier chip, depending on the application â Flip chip â Reflow, anneal o adhesive bonding â Underfilling

VERTEX /31 Rerouting l Rerouting â Adapt pad distribution between detector and electronics chips â Material: Al â Up to 4 layers â High reliability (99.8%) â Increase cost â Best to adjust pixel and amplifier size to avoid it l Dielectric choice â Inorganic »Deposited SiO 2, Si 3 N 4 »Spin-on glass (SOG) â Organic: »Polyimide â Photosensitive polyimide »Reduce complexity and cost. â Another choice for the detector: no passivation

VERTEX /31 Under Bump Metallisation (UBM) l Aluminum not suitable for direct bump bonding â Al2O3 passivation layer â Au-Al intermetallics l Process steps (mod. 1) â Sputter etching metal layers â Normal photolithography â Metal etching l Process steps (mod. 2) â Spin on 5 µm photoresist â Sputter etching metal layers â Lift off l Metal layers : â 1st: Diffusion barrier and adherence â 2nd: Soldering â 3rd: Passivation for 2nd layer l Examples: â Ti/Ni/Au â Ti/Au/Cu/Au

VERTEX /31 Bumping technologies l Evaporation through mask l Evaporation with thick photoresist l Screen printing l Stud bumping (SBB) l Electroplating l Electroless plating l Conductive Polymer Bumps

VERTEX /31 Evaporation through mask (C4) l Process steps â Mask alignment â Sequential evaporation of »Thin UBM layer: Cr/Cr-Cu/Cu/Au »Ball: Pb/Sn â Reflow into spheres l Characteristics â Proprietary of IBM â Need for a metallic mask â Pitch 200 µm â Bump height µm â Expensive

VERTEX /31 Evaporation with thick photoresist l Process steps â Spin on thick photoresist ( µm) â Sequential evaporation of »Thin UBM layer: Cr/Cr-Cu/Cu/Au »Ball: Pb/Sn â Lift off photoresist â Reflow into spheres l Characteristics â Variation of previous method â Higher pitch

VERTEX /31 Screen printing l Process steps â Stencil alignment â Solder paste deposition with a squeegee â Reflow into spheres l Characteristics â Minimum pitch: 200 µm â Stencil printing thickness: µm Same bump height â Solder pastes: »Sn/Pb, Sn/Pb/Ag, Sn/Ag, Sn/Sb »Pb free pastes: In, Pd, Sn/Ag/Cu â Most widespread â Very high yield

VERTEX /31 Stud bumping (SBB) l Process steps â Sequential creation of a ball with a ball bonder and ball bond â Overall planarisation of bumps â Optional reflow into spheres l Charactersitics â Ball material: Au (Pb free) â Min. ball size: 45 µm (3  wire  ) â Min. pitch: 70 µm â No need for UBM in substrate â Usable in single chips â No self alignment â Cheap, but low throughput Stud Bump Bonding Solder Ball Bumping SBB

VERTEX /31 Electroplating bump bonding l Process steps â Ni/Au sputtering over the whole wafer â Photolithography to delimit bump areas (thick photoresist) â Electrolytic deposition: »Cu layer »Pb/Sn bumps â Photoresist elimination â Etch wafer metalisation â Reflow into spheres

VERTEX /31 Electroplating bump bonding l Characteristics â Other bump materials: »Au »Au/Sn â The plating process can induce wafer stress â Equipment compatible with other microelectronic technologies â Minimum pitch 40 µm â Bump height µm l Difficulties: â Bump height highly dependent in current density â Variations in current density across the wafer gives non uniformity in bump height â Difficult in using thick photoresists »Deposit »Align »Exposure

VERTEX /31 Electroless plating l Process steps â Pad conditioning â Zinkation â Bump electroless deposition l Characteristics â No need for electrodes â Photolithography not required â Bump material: Ni/Au â Minimum pitch 75 µm â Bump diameter 40 µm â Bump height µm

VERTEX /31 Conductive Polymer Bumps l Process steps â Thick photoresist patterning â Conductive polymer filling â Selective polymer curing â Photoresist removal l Characteristics â Very new procedure â Minimum bump size 100 µm â Pb free â Higher contact resistance »Rc > 100 m 

VERTEX /31 Flip chip alignment l Special equipment required â Pick and place â Alignment l Accuracy better than 1/3 bump  l Alignment State of the art: â Mechanical: 5µm â Infrared: 2µm l Self alignment during reflow allows certain degree of tolerance l Industrial equipment requires wafers as substrates, not chips

VERTEX /31 CTE (ppm/ºC) Si2.6 C1.18 SiC GaAs6.86 CdTe4.9 CdZnTe4.89 Melt. Point (ºC) 57Bi 43Sn139 62Sn 36Pb 2Ag179 63Sn 37Pb183 90Sn 9.5Bi 0.5Cu Sn 3.5Ag221 80Au 20Sn280 95Pb 5Sn308 l Thermal stress: CTE mismatch â No problem with silicon detectors â Could be an issue with alternative materials Reflow l Reflow â Soft bumps (PbSn): direct reflow â Hard bumps (Au, Ni) : solder paste â High temperature step »Reflow temp. > Melt. Point + 40ºC l Use low reflow temperatures â Problems with further soldering steps of the pixel system

VERTEX /31 Adhesive bonding l Isotropic (ICA) or anisotropic (ACA) conductive adhesives l Eliminates reflow l Requires hard bumps: â Au, Au/Sn, Ni l There are anisotropic adhesive pastes and films l Advantages â Low thermal processing â Eliminates solder mask â Excellent fine pitch â No clean â Pb free l Disadvantages â Lower mechanical strength â No self-alignment »Higher accuracy of alignment â Higher electrical resistance â Higher thermal resistance â More difficult to rework

VERTEX /31 Underfilling l Optional l Curing temperature: ºC l Materials: â Silicones â Epoxies l In pixel systems it will be necessary to evaluate: â Interaction of fillers with detector surface â Radiation resistance of the materials used l Advantages â Improve reliability â Reduce thermal stress â Increase fatigue resistance â Protect from moisture and contamination â Avoid corrosion l Disadvantages â Difficults reworking â Need of a dispensing machine â Increase cost

VERTEX /31 Bump technology comparison Pb alloys can be alfa sources Min. ball size Min. Pitch Bump material UBMSubstrateComments Evaporation through mask 100 µm250 µmPb/SnCr-CuWaferNo fine pitch Screen printing100 µm200 µm Pb/Sn Sn/Ag/Cu Ti-Ni-AuWafer Most widespread Cheap Stud bumping (SBB) 70 µm45 µm Au Pb/Sn No need Wafer Chip Low throughput No self-alignment Electroplating25 µm40 µm Pb/Sn Cu/Sb/Ag/Sn Cr-Cu TiW-Cu-Au Ti-Ni-Au Wafer Need for tight control Electroless plating 40 µm70 µmNi/AuZn Wafer Chip Need for pad conditioning Conductive Polymer Bumps 100 µm150 µmPolymerCr-AuWafer High Rc Very new

VERTEX / SIA Technology Roadmap l Technology roadmap predictions l Not technological details l High pitch flip chip (< 50 µm) as needed for high resolution pixel detectors â Seems not to be of primary commercial interest in USA â It will remain at lab level until 2007 â Probably price will not decrease in short term Flip chip pitch area (µm) High performance Low cost applications

VERTEX / Japan JISSO Technology Roadmap l Similar figures to SIA Roadmap l Japan is leading Pb free bumps â For environmental reasons, but good for radiation detectors l Although not listed, electroless should also be considered l Pitch target: 50 µm Max number of pads Chip thickness (µm) Area pad pitch (µm) Bump diameter (µm) Bump height (µm) Bump materialPbSn, Au Bump formation method Bump bonding materialSnPb paste Electroplatting, Stud bumping SnPb paste, Pb free solder PbSn, Au, AgSn

VERTEX /31 Testing issues l Determine electrical properties of bump bonds â Contact resistance â Temperature variation l Determine re-routing capacitances l Leakage between bumps l Evaluate reliability of bump bonds l Contact Resistance  Very small resistance values (m  ) â Requires the use of special test structures â Contact resistance of: »Rerouting metal measurement »UBM »Bumps

VERTEX /31 Rerouting metal contact measurement l Test chip with special Kelvin contact resistance test structures â Chip metal with UBM â Flip chip to substrate through ball â UBM to substrate through ball

VERTEX /31 Contact resistance results

VERTEX /31 Other testing issues l Leakage between bumps: â Final leakage current with the system finished. â Difficult to measure â Need not only for test chips, but for test system l Bump bonding yield â Find for dead channels â Separate dead channels at the amplifier or during bonding l System reliability

VERTEX /31 Thermal issues l High density of heat generation with difficult evacuation l Bumps can evacuate heat but is not the best way l Heatsink needed â In substrate chips â In backside of flipped chip â With forced convection »Air cooled »Liquid cooled l Good thermal design l Good material choice for heat evacuation

VERTEX /31 Thermal measurements l Using specific test chips with heaters and temperature sensors l Thermal measurements â Thermal conductivities â Thermal resistances l Thermal modeling â Thermal conductivities â Heat dissipation

VERTEX /31 Example of thermal measurements l CNM MCM-D tecnology â Thermal conductivities »Si: 150 W/mK »Pb/Sn bump ball: 5 W/mK »Underfill: 0.3 W/mK »Polyimide: 0.2 W/mK â Thermal resistance »1 cm2 Si chip: 0.03 K/W »1 ball: 850 K/W »1000 ball: 0.85 K/W â Thermal model: »Heating of test flip chip without heatsink

VERTEX /31 Conclusions l Flip chip bump bonding is the perfect technology for pixel systems l Still difficulties to be solved â Pb alpha emission â Thick photoresist manipulation â Testing â Thermal behavior l Commercial interest â 50 µm pitch still not commercially available â Prices will decrease l CNM is involved in different EC projects â SUMMIT »MCM-D technology »Screen printing »Finished â CIRRµS »Jan Dec 2002 »High volume, low cost, Pitch 40 µm »Partners: Philips, CNM, CS2, Freudenberg, IMEC, TEMIC, TUB »Evaluation of different technologies