POSTER TEMPLATES BY: The ATLAS Tile Calorimeter (TileCal) at the LHC is used to measure the hadrons produced with polar angles >21 0 and the energy deposition of ~20MeV to ~1.3TeV in the detector cells. The total readout channels are ~10K and the required readout dynamic range is 16-bit. The front-end readout electronics of the ATLAS TileCal at the LHC is commercial off-the-shelf (COTS) components based, it has presented excellent performance and met the present rad-hard requirements at the LHC. However, increased radiation levels and component lifetime limits will necessitate to upgrade the TileCal front-end readout electronics for the sLHC. Another requirement is to improve the resolution of the Level-1 trigger system. This can be achieved by using digital processing on the full resolution of a digital readout to replace the current analog trigger sums. In this presentation, as a primary evaluation, we look at a design using COTS components, much as is done in the current TileCal electronics at the LHC. We believe that with the latest developed COTS components and ASIC with deep- submicron technology, significant improvements in radiation tolerance are possible. Another goal with this design is to reduce power consumptions and the number of low voltage DC power supplies used for the front-end electronics. This should facilitate the design of a less complicated, highly reliable low voltage DC power system which will be needed at the sLHC. Fig 4: Schematics of the 7-pole passive LC shaper Design of the Front-end Readout Electronics for ATLAS Tile Calorimeter at the sLHC K. Anderson 2, G. Drake 1, J-F. Genat 2, M. Oreglia 2, J. Pilcher 2, L. Price 1, F. Tang 2 1 Argonne National Laboratory, 9700 S. Cass Ave. IL 60439, USA 2 Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Ave. Chicago, IL 60637, USA IEEE, 17 th Real Time Conference, May , Lisbon, Portugal. Introduction Tile Calorimeter Detector and Readout Requirements for sLHC Tile Calorimeter Front-end Electronics Front-end Analog Readout 7-Pole Passive LC Shaper Simulation Results Performance and Rad-Hard Tests Conclusions and Future Plans Linearity and Noise Test Results --- LHC versus sLHC (Fig. 10) Tile barrel Tile extended barrels Total Front-end Readout Channels: ~10K Measured Energy Range:20MeV to 1.3TeV Maximum PMT Output Charge: ~800pC Readout Methodology: Bi-gain, 40MSPS Sampling Required Readout Dynamic Range: 17-bit (with dual 12-bit ADCs) Electronics Calibration Capability: Yes Cesium Calibration Capability: Yes System Noise:~1 count at the hi-gain output The front-end analog electronics board sits inside of each PMT block in the Tile Calorimeter. The basic readout method is continuous pulse sampling at 40MSPS. The fast leading edge PMT signal (~5ns) is shaped at first by a 7-pole passive LC shaper to a very symmetrical unipolar output pulse, which is then sent in parallel to a high-gain and a low-gain amplifiers with a gain ratio of 32. Followed by differential drivers with 2-pole active low-pass filter, the system noise bandwidth is further cut, it helps boost the system signal-to-noise ratio before feeding the signals to 40MSPS 12-bit ADCs. The shapers’ sensitivity is designed at 2V/800pC and the output pulse width is 50ns FWHM. The gain ratio of 32 extends the system dynamic range to ~17-bit with 12-bit ADCs. An on-board programmable 3-gain slow integrator is used to monitor the PMT current induced by a cesium source during detector calibration and the minimum bias current induced by the deposited energy in the cell during proton-proton colliding. The other utility circuits include precise charge injection, integrator gain controls and the interface of the front-end control bus. Fig. 1: ATLAS Tile Calorimeter. One Barrel and two end-cap sections Fig. 2: TileCal Electronics Drawer. A total of 1024 Electronics Drawers to house the readout electronics. The “zero noise”, “zero power” 7-pole passive LC shaper is designed to achieve optimal system signal-to-noise ratio and shape the PMT fast signal to a “slower” standard pulse shape that can meet the Nyquist criterion for 40MSPS digitizer. The 7-pole passive LC shaper has a bandwidth of ~12.5MHz at -3dB and an effective bandwidth roll-off slightly greater than -100dB per decade in the 1 st Nyquist zone. In the 2 nd Nyquist zone, as the bandwidth roll-off is -140db per decade, the noise mapped back from this zone can be ignored. The shaper has an output impedance of 126 ohms with a sensitivity of 2V/800pC that significantly help boost the system signal-to-noise ratio. The another advantage with a passive LC shaper is that we can directly inject charge through the capacitors at the first stage of an LC chain to perform both high-gain and low-gain calibration precisely without affecting the shaper’s characteristics. With the typical TileCal PMT signal, the shaper gives a very symmetrical unipolar output pulse of 50ns FWHM. (1) 7-pole Passive LC Shaper 7-pole Passive LC Shaper Transfer Function and Simulation Results Ideal 7-pole Shaper Transfer Function versus 7-pole passive LC shaper Transfer Function: 50ns FWHM -100dB/Decade PMT pulse Fig. 5: Shaper Transient Response Fig. 6: Shaper Bandwidth & Roll-off 7-pole LC Shaper 1X Clamping Amp 32X Clamping Amp Diff. Driver w/ 2-pole LP Filter The Integrator is designed to measure the PMT current induced by a radioactive cesium source as it traverses a hole through the scintillating tiles of the calorimeter for detector calibration. This allows equalization of the phototube gains. It will also be used to measure the phototube current induced by minimum bias proton-proton interactions at the sLHC. Because the minimum bias current in the calorimeter varies with the position of the cells, it requires that the integrator has a variable sensitivity. The integrator’s transimpedance is set by a programmable T-network resistors for 3 gains of 7.5M , 20M , 54.3M  respectively. The time constant of the integrator is required to be >10ms, which gives a ripple of <1LSB of a 12-bit ADC. The linearity for any gain settings should be < 0.3%. Intersil HFA1135 Combining bi-gain amplifiers and two 12-bit ADCs, the readout system is capable to boost its dynamic range to ~17-bits. The high-gain channel will cover signal range from 0-25pC, and the low-gain channel will cover a range of ~25pC to 800pC. (Fig. 8). However, the high-gain channel must have a quick recovering time from a 32x overdrive. The low power, high speed HFA1135 clamping amplifier is used in our design. It has a few nanoseconds overdrive recovery time. This functionality not only allows us to set the proper output level to protect downstream circuits from damage or input saturation, but also ensure a quick return to linear operation following an overdrive signal. Since the sLHC will produce collisions every 25ns, the HFA1135 will not cause any dead time because of the overdrive. The following differential driver with 2-pole low-pass active filter has a bandwidth of ~30MHz, that will further reduce the noise bandwidth to boost the system signal-to-noise ratio without significantly affecting the pulse shape. Fig. 8: Bi-gain dynamic range and resolution Shaper output Fig. 9 : ATLAS TileCal Front-end Prototypie Card for the sLHC Compared to the 3-in-1 front-end readout card that we are currently using in the ATLAS TileCal at the LHC, the new design offers significant improvements in performance. The radiation hardness tests are planned. The TileCal front-end electronics will be housed inside the detector. The rad-hard requirement at the sLHC for the front-end electronics is specified at a level of ~200Krad. We understand that the COTS components may be very challenging. Designing a rad-hard, low power and reliable TileCal front-end electronics system is essential for the sLHC upgrade. The next approach for future design will concentrate on a rad-hard, low power, high performance ASIC. In principle, the ASIC readout system will be designed with a similar methodology as the COTS- based front-end electronics. We are now in the phase of investigating both the deep-submicron technologies in BiCMOS and CMOS processes for the design. We have seen many technical challenges, such as the design of fast speed, low on-resistance analog switches for charge injection and the op-amp with ultra low leakage current for integrator. The details of the ASIC design will not be discussed in this paper. Fig. 7: Schematic of fast signal processing Fig 3: Diagram of the front-end analog readout. (3) Integrator (2) Bi-gain Clamping Amplifiers and ADC Drivers LHC Card Low-gain Linearity sLHC Card LHC Card High-gain Linearity sLHC Card LHC Card High-gain RMS noise sLHC Card LHC Card Low-gain RMS noise sLHC Card RMS Noise < 1LSB of a 12-Bit ADC RMS Noise ~1LSB of a 12-Bit ADC LC 7-pole Transfer function, each pole is in different locations, but can be designed very close.