- Software block schemes & diagrams - Communications protocols & data format - Conclusions EUSO-BALLOON DESIGN REVIEW, 18.12.2012, CNES TOULOUSE F. S.

Slides:



Advertisements
Similar presentations
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
Advertisements

DCM Embedded Software Infrastructure, Build Environment and Kernel Modules A.Norman (U.Virginia) 1 July '09 NOvA Collaboration Mtg.
Operating-System Structures
 Guy Jacob  Roee Shapiro – Project A Spring, 2008 INFINI DRIVE  Project Supervisor: Hai Vortman  Lab Chief Engineer: Dr. Ilana David.
OS Fall ’ 02 Introduction Operating Systems Fall 2002.
1 ITC242 – Introduction to Data Communications Week 12 Topic 18 Chapter 19 Network Management.
Architectural Support for Operating Systems. Announcements Most office hours are finalized Assignments up every Wednesday, due next week CS 415 section.
An 8051 Based Web Server Project by Mason Kidd Advised by Dr. Schertz.
Modifying the SCSI / Fibre Channel Block Size Presented by Keith Bonneau, John Chrzanowski and Craig O’Brien Advised by Robert Kinicki and Mark Claypool.
Cs238 Lecture 3 Operating System Structures Dr. Alan R. Davis.
Input/Output and Communication
1 What is an operating system? CSC330Patricia Van Hise.
Wireless Data Acquisition for SAE Car Project by: J.P. Haberkorn & Jon Trainor Advised by: Mr. Steven Gutschlag.
March 2003 CHEP Online Monitoring Software Framework in the ATLAS Experiment Serguei Kolos CERN/PNPI On behalf of the ATLAS Trigger/DAQ Online Software.
Module 1: Database and Instance. Overview Defining a Database and an Instance Introduce Microsoft’s and Oracle’s Implementations of a Database and an.
EUSO-BALLOON CDR – Agenda (I). Internal interfaces overview Batteries and Low Voltage power Supplies PDM interfaces DP interfaces HK Interfaces List of.
Copyright ©: Nahrstedt, Angrave, Abdelzaher
March 2004 At A Glance ITOS is a highly configurable low-cost control and monitoring system. Benefits Extreme low cost Database driven - ITOS software.
Lecture 12 Today’s topics –CPU basics Registers ALU Control Unit –The bus –Clocks –Input/output subsystem 1.
USB host for web camera connection
Introduction to USB Development. USB Development Introduction Technical Overview USB in Embedded Systems Recent Developments Extensions to USB USB as.
- Where are the entry points of the instrument - Physical External links - Overview of the External Interfaces - Status - Conclusion EUSO-BALLOON DESIGN.
Input/Output mechanisms
Input/OUTPUT [I/O Module structure].
OPERATING SYSTEM OVERVIEW. Contents Basic hardware elements.
Microprocessor-based Systems
Hardware Definitions –Port: Point of connection –Bus: Interface Daisy Chain (A=>B=>…=>X) Shared Direct Device Access –Controller: Device Electronics –Registers:
1 Lecture 20: I/O n I/O hardware n I/O structure n communication with controllers n device interrupts n device drivers n streams.
Windows Operating System Internals - by David A. Solomon and Mark E. Russinovich with Andreas Polze Unit OS6: Device Management 6.1. Principles of I/O.
Three fundamental concepts in computer security: Reference Monitors: An access control concept that refers to an abstract machine that mediates all accesses.
 Project Description & Goals  Hardware Used  Circuitry & Connections  Communication  Software & Programming  End Result.
Design and implementation of under water data collection and communication Sreynoch Chin Advisor: Professor J. Hedrick.
The MPC Parallel Computer Hardware, Low-level Protocols and Performances University P. & M. Curie (PARIS) LIP6 laboratory Olivier Glück.
Chapter 2: Operating-System Structures. 2.2 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 2: Operating-System Structures Operating.
Computer Architecture Lecture10: Input/output devices Piotr Bilski.
G. Maron, Agata Week, Orsay, January Agata DAQ Layout Gaetano Maron INFN – Laboratori Nazionali di Legnaro.
ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw.
SXC Software interfaces1 SXC: SW interfaces Ground segment SpacecraftDetectorTelescope TelecommandsTelemetry Cmd & hk parameters- conversion SpacecraftTelecommandsTelemetryProtocolBandwidthcoverage.
Online Calibration of the D0 Vertex Detector Initialization Procedure and Database Usage Harald Fox D0 Experiment Northwestern University.
I/O Computer Organization II 1 Interconnecting Components Need interconnections between – CPU, memory, I/O controllers Bus: shared communication channel.
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
Online Software 8-July-98 Commissioning Working Group DØ Workshop S. Fuess Objective: Define for you, the customers of the Online system, the products.
Overview of DAQ at CERN experiments E.Radicioni, INFN MICE Daq and Controls Workshop.
1 © 2005 Cisco Systems, Inc. All rights reserved. 111 © 2004, Cisco Systems, Inc. All rights reserved. CNIT 221 Security 2 ver.2 Module 8 City College.
L/O/G/O Input Output Chapter 4 CS.216 Computer Architecture and Organization.
McGraw-Hill©The McGraw-Hill Companies, Inc., 2004 Connecting Devices CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL Department of Electronics and.
Bart Hommels (for Matthew Wing) EUDET ext. steering board JRA3 DAQ System DAQ System Availability updates: – DIF: Detector Interface – LDA:
IPHC - DRS Gilles CLAUS 04/04/20061/20 EUDET JRA1 Meeting, April 2006 MAPS Test & DAQ Strasbourg OUTLINE Summary of MimoStar 2 Workshop CCMOS DAQ Status.
- Overview of the subsystems - The Photodetector Module and its components - The Data Processing and its components - The Power Pack - Summary of subsystems.
Chapter 13 – I/O Systems (Pgs ). Devices  Two conflicting properties A. Growing uniformity in interfaces (both h/w and s/w): e.g., USB, TWAIN.
CAN-Bus Logger Characterization presentation Apr. 19, 2009 Elad Barzilay Idan Cohen-Gindi Supervisor: Boaz Mizrahi.
NS Training Hardware Traffic Flow Note: Traffic direction in the 1284 is classified as either forward or reverse. The forward direction is.
Management of the LHCb Online Network Based on SCADA System Guoming Liu * †, Niko Neufeld † * University of Ferrara, Italy † CERN, Geneva, Switzerland.
5 June 2002DOM Main Board Engineering Requirements Review 1 DOM Main Board Software Engineering Requirements Review June 5, 2002 LBNL Chuck McParland.
TRIO-CINEMA 1 KHU, 10/08/2010 Ground Support Software Yong-ho Kim 22 Feb 2011 School of Space Research Kyung Hee University.
بسم الله الرحمن الرحيم MEMORY AND I/O.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
1 DAQ.IHEP Beijing, CAS.CHINA mail to: The Readout In BESIII DAQ Framework The BESIII DAQ system consists of the readout subsystem, the.
LonWorks Introduction Hwayoung Chae.
Data Processor Status Hardware Giuseppe Osteria INFN Napoli Paris, October 12, 2012 Euso Balloon 8th progress meeting Giuseppe Osteria INFN Sezione di.
Scalable Readout System Data Acquisition using LabVIEW Riccardo de Asmundis INFN Napoli [Certified LabVIEW Developer]
Team Members: ECE- Wes Williams, Will Steiden, Josh Howard, Alan Jimenez Sponsor: Brad Luyster Honeywell Network Traffic Generator.
I/O SYSTEMS MANAGEMENT Krishna Kumar Ahirwar ( )
Chapter 2: System Structures
AT91RM9200 Boot strategies This training module describes the boot strategies on the AT91RM9200 including the internal Boot ROM and the U-Boot program.
ATA over internet.
UNIT-III Pin Diagram Of 8086
Requirements Definition
Chapter 13: I/O Systems.
Presentation transcript:

- Software block schemes & diagrams - Communications protocols & data format - Conclusions EUSO-BALLOON DESIGN REVIEW, , CNES TOULOUSE F. S. Cafagna I.N.F.N., Sezione di Bari, Bari (Italy) Software CPU status

CDR – A brief overview & block scheme CDR – Software CPU status2 User Interfaces Layer. Telemetry, Console & GUI, Remote access, etc. etc. Hardware Interfaces Layer. Drivers, Readout units, etc. etc. Manager Layer. Run Control FSM, Messages, Configurations etc. etc. User Space Kernel Space

CDR – From the DP block scheme … CDR – Software CPU status3

CDR – CPU has been extracted, interfaces … CDR – Software CPU status4

CDR – … & communication factorized CDR – Software CPU status5

CDR – CPU software block scheme CDR – Software CPU status6 Processes Managers layer Hardware Interfaces & drivers layers User Interfaces & Telemetry layer

CDR – CPU software block scheme Control Manager (Run Control) Implements the Run Control and supervises the whole software operations. Message Manager Marshals and routes messages between software blocks. Data Manager Provides services to efficiently manage the data handling, storage and transmission to ground. Event Builder Merges CCB, CLKB and all other relevant data into an event frame and check for consistency. Configuration Manager Stores, updates and handles configurations for all subsystems and software blocks. Log Manager Provides a log service to all the software blocks that need it. CDR – Software CPU status7

CDR – CPU software block scheme Readout Unit Interface (RUI) Communicates with blocks external to the CPU and manages the data & command flows to and from them. Data Unit Interface (DUI) It is a special RUI dedicated to the data I/O. It is directly interfaced to the SATA or the Ethernet interfaces. Telemetry User Interface (TUI) Handles the command and data transmissions between the telemetry system (SIREN) and the CPU. User Interface (UI) Implements the communications with user and controls when the telemetry system is not connected. CDR – Software CPU status8

CDR – CPU software blocks scheme CDR – Software CPU status9 Transfer data to disk &/or telemetry Polling the CLK for triggers Request data from CCB, CLK

CDR – Run control Finite State Machine (FSM) CDR – Software CPU status10

CDR – Run control Finite State Machine (FSM) CDR – Software CPU status11

CDR – User Scenario: Normal Data Acquisition CDR – Software CPU status12

CDR – User Scenario: Normal Data Acquisition CDR – Software CPU status13 User changes detector parameters User operates runs and calibrations Quicklook & Telemetry

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status14

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status15

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status16

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status17

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status18

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status19

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status20

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status21

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status22

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status23

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status24

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status25

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status26

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status27

CDR – Activity diagram: Normal Data Acquisition CDR – Software CPU status28

CDR – Communications with HK Communication between CPU and HK. Low level protocol: RS422; serial point to point, master-slave protocol. HK is the slave and respond only upon CPU request. CRC16 will be used to check for data corruption during transmission from and to HK. HK data format Data are 16 bit words while commands are encoded into a 8 bit word. The packet size range from a minimum of 5 Bytes to a maximum of 8 Bytes. CDR – Software CPU status29

CDR – Communications with CCB (PDM) Communications between CPU and CCB Low level protocol: SpaceWire; full-duplex. Messages transmitted by the CCB to the CPU includes a CRC-32 (IEEE 802.3, Ethernet). CCB interfaces the CPU with the PDM and the SPACIROCs attached to the latter. Both command and data packets must be exchanged to configure the boards and chips, and readout physics data (~330kB/event). CCB (PDM) data format Commands are simple actions on the boards or write/read register requests on boards and chips. Different commands may have different associate parameters (data). CDR – Software CPU status30

CDR – Communications with CLKB Communications between CPU and CLKB Low level protocol: SpaceWire; full-duplex. Messages transmitted by the CLKB to the CPU includes a CRC-32 (IEEE 802.3, Ethernet). CLKB interfaces the CPU with the GPS board. Both command and data packets must be exchanged to configure the boards, and readout GPS and trigger data (~800B/event). CLKB data format Both trigger status and GPS data are transmitted by the CLKB to the CPU. Trigger status data can be transmitted standalone: Or togheter with the GPS ones: CDR – Software CPU status31

CDR – Conclusions −Hardware interface backbone layer developed (Spacewire, RS422) and extensive performance tests, to monitor failure rates and spot bottlenecks, are in progress. −The low level drivers and communication protocols have been tested on the flight CPU and the data acquisition chain proven to work. −The most critical part was related to the SpaceWire driver that is in charge for the bulk data exchange between the CPU and CCB. This driver is actually understood and the data transfer rate between the CCB and the CPU is almost the maximum one reachable with the SpaceWire protocol. −The low level packet formats of both commands and data have been defined for all DP components. −Continuous feedback to and from the developers to define hardware block working modes, configuration parameters, command lists etc. etc., and debug and fine tune the firmware of the HK, CCB and CLKB. CDR – Software CPU status32