©Alex Doboli 2006 Switched Capacitor Blocks Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook

©Alex Doboli 2006 Overview of the Chapter Introduction to SC circuits Programmable SC blocks in PSoC SC principle: controlled movement of charge Electrical nonidealities: circuit nonidealities, non-zero switch resistance, channel charge injection, clock feedthrough Basic SC blocks: gain amplifier, programmable gain amplifier, comparator, integrator, differentiator PSoC’s programmable SC blocks: –Type C and Type D SC blocks –Programming (registers)

©Alex Doboli 2006 Introduction to SC Techniques SC techniques : –Integrated capacitors are easier to fabricate than resistors –Average resistance approximated through charge movement I = V / R Q = C V I average = Q f s = C V f s =>R eq = 1 / C f s

©Alex Doboli 2006 Introduction to SC Techniques Constraints: –Switches Ф 1 and Ф 2 can never be closed at the same time –Switch Ф 1 must have time to open before switch Ф 2 closes –Switch Ф 2 must have time to open before switch Ф 1 closes –Frequency f s must allow enough time for the circuits to fully charge and discharge

©Alex Doboli 2006 Non-idealities in SC Circuits Non-zero on-resistance of MOSFETs: d V c (t) / d t = I D (t) / C Linear: d V c (t) / d t =  C ox W [(V DD – V c (t) - V th )(V in – V c (t)) – (V in – V c (t)) 2 / 2] / 2 LC V c (t) =  2 K exp (A V in t) – A exp (A V in t) + exp (kt + K[1]))  V in / (A exp (A V in t) + exp (K t + K[1]) A =  C ox W / 2 L C K = A (V DD – V th ) Saturation:d V c (t) / d t =  C ox W [(V DD – V c (t) - V th )(V in – V c (t)) – (V in – V c (t)) 2 / 2] / 2 LC V c (t) = [(A t – C[1]) (V DD - V th ) - 1] / (A t – C[1]) V c (0) = 0 => C[1] = - 1 / (V DD - V th ) V c (t) = V DD – V th – 1 / (a t – C[1])

©Alex Doboli 2006 Non-idealities in SC Circuits Channel charge injection: Q channel = W L C ox (V DD – V in - V th )  V c = W L C ox (V DD – V in - V th ) / C Trade-offs: –Accuracy vs. speed (small W helps accuracy but decreases speed)

©Alex Doboli 2006 Non-idealities in SC Circuits Clock feedthrough: –Capacitive coupling through C gd  V out = - C gd,2  V Φ2 Trade-offs: –Accuracy vs. speed (small W lowers coupling but lowers speed too)

©Alex Doboli 2006 SC Fixed Gain Amplifier Characteristics: acquisition phase transfer phase

©Alex Doboli 2006 Acquisition & Transfer Phase  Q = V in C A  V out = -  Q / C F Gain = - C A / C F

©Alex Doboli 2006 Autozero Adjustment Q A i = V offset C A Q F i = V offset C F Q A f = (V in – V offset ) C A Q F f = (V offset – V out f ) C F Q A i + Q F i = Q A f + Q F f V out f = V offset – [(C A + C F ) V offset – C A (V offset - V in )] / C F V out f = - C A / C F V in

©Alex Doboli 2006 SC Selectable Gain Polarity Amplifier

©Alex Doboli 2006 SC Comparator

©Alex Doboli 2006 SC Integrator

©Alex Doboli 2006 SC Integrator During acquisition: Q = V in C A During transfer: Q tot = Q’ + V in C A V out (t) = V out (t – T s ) + C A / C F V in [V out (t) - V out (t – T s )] / T s = f s C A / C F V in d V out (t) / dt = C A / C F f s V in Integrator gain: C A / C F f s

©Alex Doboli 2006 SC Differentiator

©Alex Doboli 2006 Improved Reference Selection

©Alex Doboli 2006 Improved Reference Selection Ground reference: V out = V in C A / C F V ref+ reference: V out = (V in – V ref+ ) C A / C F V ref- reference: V out = (V in – V ref- ) C A / C F Integrator gain: C A / C F f s

©Alex Doboli 2006 Two Bit ADC

©Alex Doboli 2006 Two Bit ADC 1.V in > V ref+ 2.V in 0 3.V in V ref- 4.V in < V ref-

©Alex Doboli 2006 Analog to Digital Conversion

©Alex Doboli 2006 Analog to Digital Conversion 1.Reference is V ref+ if comparator output is 1 2.Reference is V ref- if comparator output is 0 3.V out i = 0 4.Switch cycle is performed n times 5.Comparator output is 1 a number of a times V out = C A / C F [n V in – a V ref+ - (n – a) V ref- ] For V ref+ = - V ref- = V ref : V in = V ref (2 a - n) / n + V out C F /[ n C A ] V in = V ref (2 a - n) / n Resolution: V ref 2 / n

©Alex Doboli 2006 Switched Capacitor PSoC Blocks Each column: analog bus, comparator bus, clocks Φ 1 and Φ 2

©Alex Doboli 2006 PSoC Type C Block

©Alex Doboli 2006 PSoC Type C Block 1.Control registers: ASCxxCR0, ASCxxCR1, ADCxxCR2, ASCxxCR3 1.Functionality (gain, integrator, comparator) 2.Input & output configuration 3.Power mode 4.Sampling procedure (positive / negative gain) 2.OpAmp: 1.4 power modes (off, low, medium, high) 2.Programmed through bits PWR (bits 1-0 of ASCxxCR3) 3.Functionality programmed through bits FSW1 and FSW0 3.Bit FSW1: 1.FCap connected or not (gain/integrator or comparator) 2.Bit 5 of ASCxxCR3 4.Bit FSW0: 1.FCap discharged or not (gain or integrator) 2.Bit 4 of ASCxxCR3

©Alex Doboli 2006 PSoC Type C Block 5.Programmable matrix arrays: ACap, BCap, CCap, FCap 1.ACap value programmed through bits 4-0 of ASCxxCR0 2.Value: 0 – 31 units (1 unit ~ 50fF) 3.Autozero bit: 1.Autozeroing during Φ 1 2.Bit 5 of ASCxxCR2 4.Asign bit: positive or negative gain 1.Bit 5 of ASCxxCR0 2.Positive gain: input sampled on clock Φ 1 3.Negative gain: input sampled on clock Φ 2 4.Reference selection 6.BCap:  BCap capacitor value: 0 – 31 units  Bits 4 – 0 in ASCxxCR1 7.CCap: 1.CCap capacitor value: 0 – 31 units 2.Bits 4-0 in ASCxxCR2

©Alex Doboli 2006 PSoC Type C Block 8.FCap:  Value programmed through bit 7 of ASCxxCR0  Value: 16 or 32 units 9.Programmable inputs: 1.Inputs to ACap, BCap, CCap are programmable 1.Bits 7-5 of ASCxxCR1 2.Reference to ACap is also programmable 1.Bits 7-6 of ASCxxCR3 2.AGND, V ref+, V ref-, comparator output (RefHi if comparator output is high, and RefLo if comparator output is low)

©Alex Doboli 2006 Programmable ACap Inputs ACMuxASC10ASC21ASB12ASC23 000ACB00ASD11ACB02ASD13 001ASD11ASD20ASD13ASD22 010RefHi 011ASD20VtempASD22ABUS3 100ACB01ASC10ACB03ASC12 101ACB00ASD20ACB02ASD22 110ASD11ABUS11ASD13ABUS3 111P2[1]ASD22ASD11P2[2] ACMux: bits 7-5 of ASCxxCR1

©Alex Doboli 2006 Programmable BCap Inputs BCMuxASC10ASC21ASB12ASC23 00ACB00ASD11ACB02ASD13 01ASD11ASD20ASD13ASD22 10P2[3]ASD22ASD11P2[0] 11ASD20TrefGNDASD22ABUS3 BCMux: bits 3-2 of ASCxxCR3

©Alex Doboli 2006 Programmable CCap Inputs ACMuxASC10ASC21ASB12ASC23 000ACB00ASD11ACB02ASD13 001ACB00ASD11ACB02ASD13 010ACB00ASD11ACB02ASD13 011ACB00ASD11ACB02ASD13 100ASD20ASD11ASD22ASD13 101ASD20ASD11ASD22ASD13 110ASD20ASD11ASD22ASD13 111ASD20ASD11ASD22ASD13 ACMux: bits 7-5 of ASCxxCR1

©Alex Doboli 2006 PSoC Type C Block 10.Programmable outputs: 1.Bit AnalogBus: 1.Output to analog buffer 2.Bit 7 of ASCxxCR2 2.Bit CompBus: 1.Connects comparator output to digital block inputs 2.Bit 6 of ASCxxCR2 11.Clocking scheme: 1.Bit ClockPhase: 1.Bit 6 of ASCxxCR0 2.External Φ 1 or Φ 2 is internal Φ 1

©Alex Doboli 2006 Type D Switched Capacitor Blocks

©Alex Doboli 2006 Type D Switched Capacitor Blocks Differences:  CCap connected to the output, which connects to the suming node of the next SC C block (biquad filters)  Switch BSW: BCap is either SC or fixed capacitor  BCap connected to the summing node  AnalogBus switch connects OpAmp output to analog buffer  CompBus switchconnects comparator to the digital blocks  BCap programmable capacitor sampled on Φ 2

©Alex Doboli 2006 Example: Differential amplifier with common mode input V differential = PosInput – NegInput V common = (PosInput + NegInput) / 2

©Alex Doboli 2006 Example: Differential amplifier with common mode input

©Alex Doboli 2006 Analog to Digital Conversion

©Alex Doboli 2006 Isolated Analog Driver