Chapter 5 Arithmetic Logic Functions

Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR, SHIFT etc: Logic functions  ADD, SUBTRACT, etc. Arithmetic functions

Page 3 Iterative Functions and circuits  Multi-bit logical functions (AND, OR, etc.) have functional independence between bits  E.G. for a multi-bit AND where we want to find F= A. B we have  On the other hand, Arithmetic functions DO have dependence bit to bit (carry or borrow)  The functions are the same at each bit position but dependent on the previous bit  These functions are known as ITERATIVE

Page 4 Iterative Functions cell or stage i-1 cell or stage i cell or stage n-1 cell or stage 0 BiBi AiAi FiFi XiXi YiYi B i-1 A i-1 F i-1 X i-1 Y i-1 B0B0 A0A0 F0F0 X0X0 Y0Y0 B n-1 A n-1 F n-1 X n-1 Y n-1...

Page 5 Networks for Binary Addition Half Adder - adds two bits together; generates sum and carry Half-adder Schematic Carry Sum A i B i Ai Bi Sum Carry Ai Bi Sum = Ai Bi + Ai Bi = Ai + Bi Ai Bi Carry = Ai Bi

Page 6 Networks for Binary Addition Full Adder - adds three bits, one being a carry bit Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder stage 0 B0B0 A0A0 S0S0 C1C1 stage 1 S1S1 C2C2 stage 0 S2S2 C3C3 stage 0 S3S3 C4C4 B1B1 A1A1 B2B2 A2A2 B3B3 A3A3 C0C0

Page 7 Networks for Binary Addition Full Adder S = C in xor A xor B C out = B C in + A C in + A B But we can also write in long form =AB+C in A’B+C in AB’ = C in (A xor B) + A B A B Cin S Cout A B Cin A B C in S C Out x

Page 8 Networks for Binary Addition Full Adder/Half Adder implementation Alternative Implementation: 5 Gates Standard Approach: 6 Gates A A A B B B Cin S Cout Half Adder A B Half Adder A + B Cin A + B + Cin SS Cout Cin (A+ B) A B S Cout Cout= A B + Cin (A xor B)

Page 9 Networks for Binary Addition

Page 10 Parallel(Ripple-Carry) Adder

Page 11 Parallel Adder-Subtractor  Parallel Adder-Subtractor with 2’s complement numbers:  To subtract, we take the 2’s complement of the second number and add  To take 2’s complement use the approach: Take 1’s complement(Complement bit by bit) and add 1.  To add 1, we will use the carry-in to the rightmost FA.  Assume a select line called Add/subtract

Page 12 Networks for Binary Addition Parallel Adder/Subtractor - assumes 2’s complement representation A - B = A + (-B) = A + B + 1 Remember subtraction is the same as taking the 2’s complement and adding,so if add/subtract=1, complement b and add 1 from the rightmost Cin 2x1 mux

Page 13 Networks for Binary Addition  The Propagation Delay in Above Circuit:  3 gate delays for each full adder, but waits for 2 gate delays  For a 32 bit adder/subtractor, longest total delay is 32*2+1= 65 gate delays(will show in the next slide)  Too long-should be a shorter way  Assume A, B and C0 are presented to the input at the same time and all gates have the same delay

Page 14 Networks for Binary Addition Carry Lookahead Circuits - making things fast Critical delay: the propagation of carry from low to high order stages late arriving signal two gate delays to compute Cout 4 stage adder final sum and A 0 B 0 C 0 S A 1 B 1 C S A 2 B 2 C S A 3 B 3 C S C A A B B Calculated in parallel

Page 15 Networks for Binary Addition Carry Lookahead Logic Carry Generate G i = A i B i must generate carry when A = B = 1 Carry Propagate P i = A i xor B i carry in will equal carry out here S i = A i xor B i xor C i = P i xor C i C i+1 = A i B i + C i (A i xor B i ) C i+1 = G i + C i P i Sum and Carry can be reexpressed in terms of generate/propagate: Idea: each carry can be expressed in terms of Ai, Bi and C 0

Page 16 Networks for Binary Addition Carry Lookahead Logic Reexpress the carry logic as follows: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0!

Page 17 Networks for Binary Addition Carry Lookahead Implementation Adder with Propagate and Generate Outputs Increasingly complex logic C0 G3 1 gate delay Ci 2 gate delays Bi Ai 1 gate delay C0 P0 G0 C1 C0 P0 G0 P1 G1 C2 P0 G0 P1 G1 P2 G2 C3 C0 P0 G0 P1 G1 P2 G2 P3 C4

Page 18 Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead Carry lookahead logic generates individual carries sums computed much faster

Page 19 Ripple Carry adder Carry-save adder Carry-lookahead unit Partial Full Adder

Page 20 Networks for Binary Addition  Propagation Delay in CLA Adder:  Assume a 4-bit adder  Since each carry will be generated in with a 2-level And-or network, there will be a delay of 2 in CLA unit  Other delays: 2 in PFA  So total delay: 4  Ripple carry delay: was 8

Page 21  When the number of bits increase, the savings become more appearent but the CLA fan-in will increase unacceptably  What to do? Use cascaded approach

Page 22 Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead 4 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 16 bits

Page 23 BCD Addition Decimal digits 0 thru 9 represented as 0000 thru 1001 in binary Addition: 5 = = = 8 5 = = = 13! Problem when digit sum exceeds 9 Solution: add 6 (0110) if sum exceeds 9! 5 = = = = 1 3 in BCD 9 = = = 16 in binary 6 = = 1 6 in BCD

Page 24 BCD Addition Adder Design Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

Page 25 Incrementing and Decrementing by 1  Use ‘value fixing’  İf you want S= A+1, then use adder/subtractor as:  A= A, B=0 Cin= 1, function: add  How about S= A-1?  A=A, B= 00001, Cin=0, Fn: subtract Or, B= , Cin=0, fn: add  May have inc/dec in the same circuit  Make at home

Page 26 Multiplication and Division by Constants  Shift function: a word can be shifted right or left as many positions as you like with proper circuitry  For a binary number, shifting left one digit means dividing by 2! Shifting right means multiplying by 2!  But be careful with inserted digits.  Will study later with shift registers.