Data acquisition system on Advanced TCA M. Nomachi and S. Ajimura Osaka University, Japan CAMAC – FASTBUS – VME / Compact PCI What ’ s next?

ATCA JAN Rack Crate Module Chip Memory Mapped I/O CPU Network DAQ architecture & Downsizing Memory Mapped I/O CPU Network CPU Network

ATCA JAN CPU: merits and demerits Merits –Scalable, easy to communicate –Data base access Demerits –Boot –Overhead –Maintenance

ATCA JAN Rack Crate Module Chip Memory Mapped I/O CPU Network DAQ architecture We choose memory mapped I/O in a crate. It makes easy to maintain CPU. There were many bad experiences on embedded CPUs.

ATCA JAN 産業界の動向 VME –6U Euro card DIN connector –BUS Compact PCI –6U Euro card metric connector –BUS ATCA –8U Euro card metric connector –Serial link

ATCA JAN From Schroff

ATCA JAN-20067

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10 There are 4 ports for one channel. One port has one output and one input. In order to make signal extraction easy, 2 ports are used. (SpW uses 2 ports) The other 2 ports are to extend band width. It makes possible to use 4-layers PCBs.

ATCA JAN From Schroff

ATCA JAN

ATCA JAN Advanced TCA Features –-48V DC power supply and on board DC converter for any voltages required. –8U x 280 mm –Dual Star point to point differential connection –No definite protocol. VME back plane is for VME protocol. While, ATCA back plane is only defined as 100 ohm differential. Any protocol can use ATCA back plane. ( for example, ATCA for physics instrumentation)

ATCA JAN Read out module Trigger module Front-end module DAQ system Front-end Pipe-line buffer readout buffer Trigger logic Trigger control Global trigger Readout control network Second level trigger CPU To event builder

ATCA JAN Dual star connection Trigger module Read out module Front-end module Front-end module Front-end module Front-end module Front-end module Asynchronous signals (4 lines) Trigger/Reset Local trigger/Busy SpaceWire link (4 lines) CPU (T-kernel)

ATCA JAN Serial data transfer フロントエンドで使用するためには フロントエンドの小規模なＦＰＧＡに実装できる簡単 なプロトコル。 多くのシリアル転送ではクロックの再構築のためのＰＬＬが必要であるが、フロ ントエンドで使用するにはＰＬＬがなくても動作するプロトコルが望ましい。 高速レスポンスを実現するための短い遅延時間。 パイプライン処理を行わないフロントエンドでは遅延時間がそのまま Dead Time となってしまう。このため余計な処理を行わない単純なプロトコルが望ましい。 ノイズ源とならない信号レベル。 デジタル信号の遷移はアナログ系のノイズ源となる。このため、ＬＶＤＳ等、振 幅の小さい信号レベルが望ましい。

ATCA JAN

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003 非同期に動作するため、時間情報を保存して送ることが可能

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2003

ATCA JAN Steve Parkes 2005

ATCA JAN Steve Parkes 2005

ATCA JAN Steve Parkes 2005

ATCA JAN Steve Parkes 2005

ATCA JAN Steve Parkes 2005

ATCA JAN Steve Parkes 2005

ATCA JAN Write Operation Write Request Write Data Request Write Command Write Reply Write Complete Confirmation Source Destination Write Data Authorisation Write Data Indication Steve Parkes 2005

ATCA JAN Read Operation Read Request Read Data Request Read Command Read Reply Read Data Confirmation Source Destination Read Data Response Steve Parkes 2005

ATCA JAN SpaceWire Remote Memory Access Protocol (RMAP) –RMAP is a protocol on the SpaceWire standard. –Register access has large overhead. –Block transfer works almost full speed. –It meets the requirements. Good enough. –PCI express and the other protocol may also meet the requirements. However, they may use too much logic (x10) for front-end FPGAs.

ATCA JAN Interrupt on VME bus Interrupter Interrupt handler Interrupt Request Broadcast Read Vector Communication between strangers.

ATCA JAN User program Device Send return address Device access Wake up message RMAP read processing Response in 10~100 micro sec

ATCA JAN Interrupt register(event flag) Return address timer Wait event Wake up message Read wake up message -1 : Busy. Another process is already waiting. 0: Event already exist. n>0 : Event occurs after “n” tick. Write interrupt register 0 : cancel Hardware implementation

ATCA JAN ATCA crate One crate holds 96ch of 500MHz FADCs. Total power is expected to be 260 W.

ATCA JAN Virtual CAMAC on serial data link One crate holds 96ch of 500MHz FADCs. Total power is expected to be 260 W. Crate controller Serial data way

ATCA JAN Trigger module 16 LVDS in 16 LVDS out 8 NIM in 8 NIM out Power consumption is about 10W Cyclone EP1C12 for trigger logic Cyclone EP1C6 for SpW 100Mbps SpW

ATCA JAN MHz FADC Cyclone EP1C6 Cyclone EP1C12 for router 100Mbps SpW (8~9 MB/s from the module) Readout buffer with 128Mb SDRAM waiting second level trigger 8 ch analog input FADC mezzanine card is developed at KEK (FINESSE format) Power consumption is About 20W

ATCA JAN Summary SpaceWire Remote Memory Access Protocol provides compact and flexible interconnection in a module and inter- module connection. Advanced TCA provide dual star LVDS connections. They are good to be applied for DAQ system Downsizing may continue. –We might have another solution in the future.