Bandpass filter on FPGA Student Vitaly Zakharenko Supervisor Mony Orbach Semester Spring 2007 Duration single semester

Project Goals Programming Virtex II Pro FPGA on a development board to perform bandpass filtering.

BPF unit description Variable passband width and frequency, chosen out of a finite predefined set of values; Two inputs in addition to the signal input to allow the above; Communication with the BPF unit via Simulink environment only;

General Implementation Steps Obtaining FIR bandpass filter coefficients for each bandwidth/center frequency specification via FDATool of Matlab; Realization of the filter in Simulink using Xilinx blockset; Implementation via System Generator.

Simulink Realization Details Way #1 Adaptation from the BPF design in the Xilinx workshop, i.e. from a fully sequential MAC (Multiply-Accumulate) engine design; Using several MAC engines in parallel to provide for optimal trade off between sampling rate and FPGA area.

Current Design I Fully sequential MAC FIR Additional input specifying the filter in use Signal Input Data Out Reg Data In MAC unit 256 Loops needed to process samples FIR based on MAC unit

Current Design II Up to 31 FIR filters of up to 255 taps are switched between via the additional input; Each filter is of a different bandwidth and passband frequency; The filter coefficients are stored on the FPGA; The design allows rapid switch between filters of different specifications, since no reload of coefficients needed;

Using DAFIR or any one of the many FIR implementation blocks in Xilinx blockset in Simulink Simulink Realization Details Way #2

Testing Testing in Simulink via Hardware Co- Simulation.

Project schedule Current state of the project: one implementation complete. May 2007 Week I : testing the current implementation; Week II : testing the current implementation; Week III: improving the performance, possibly designing a different implementation, testing its performance; Week IV: introducing changes, speeding up the design and testing.