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Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Started at: Winter 2012 Duration: Semester
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What is SAT Reminder - description and goals Flow diagram Initial circuit diagram Resources usage and times Example simulation results Live Presentation Milestones Gantt diagram
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Boolean Satisfiability Problem Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? e.g., given the formula f=(x1 ˅ x3 ˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’
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Description: Hardware based SAT Solver Goals: Implementing SAT instances into FPGA Measuring build and run times for benchmark examples Implementation Time as function of SAT complexity graph Enabling further development of fast hardware based SAT Solver
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Conversion Synthesis DeviceProgrammer Running SAT Solver
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clk en F sOUT timeOUT
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For SAT instance of 20 variables and 91 clauses 155 Logic Elements Compile design time : 40 seconds For SAT instance of 1000 variables and 4250 clauses 7110 Logic Elements Compile design time : 43 minutes *Clock frequency is 50M [Hz]
![ For SAT instance of 20 variables and 91 clauses 155 Logic Elements Compile design time : 40 seconds For SAT instance of 1000 variables and 4250 clauses 7110 Logic Elements Compile design time : 43 minutes *Clock frequency is 50M [Hz]](http://images.slideplayer.com/32/10017552/slides/slide_7.jpg " For SAT instance of 20 variables and 91 clauses 155 Logic Elements Compile design time : 40 seconds For SAT instance of 1000 variables and 4250 clauses 7110 Logic Elements Compile design time : 43 minutes *Clock frequency is 50M [Hz]")
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For SAT instance of 20 variables and 91 clauses Satisfying input: 00101011011101000000
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Whats next: Testing some benchmark problems Collecting timing results Creating a detailed graph of times vs. “size”.
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