Real Time Image Feature Vector Generator Employing Functional Cache Memory for Edge Takuki Nakagawa, Department of Electronic Engineering The University of Tokyo, Japan and Tadashi Shibata, Department of Electrical Engineering and Information Systems The University of Tokyo, Japan ©2009 IEEE Vishesh Kalra EE Vishesh Kalra EE

I NTRODUCTION Image Processing requires three major stages: 1>Extracting features from input image. 2>Summarizing them as a Feature Vector. 3>Classification of Feature Vectors. The Concern of this paper is to carry out the Second stage.

Introduction contd. Edge Information extracted from an image plays a central role in image perception. In this paper, four directional edges are extracted from 64x64 local image (recognition window) using 5x5 filtering kernels of an input image of size 256x256. In order to scan the entire image, recognition window has to scan pixel to pixel from top to bottom by shifting itself.

Earlier Paper Edge flag detection from each pixel location is carried out at every clock cycle and edge flag bits are temporarily stored in an array of 64x64 shift registers to generate a histogram. When the recognition window moves, the edge data are shifted accordingly in the shift registers. As a result 64-element feature vector is generated in every 64 clock cycles. With this Architecture it has become possible to generate 1.5x10^6 feature vectors/sec at a frequency of 100 MHz.

Vector Generation Algorithm Edge filtering is carried out in 4 directions i.e. Horizontal, Vertical, +45 and -45 degrees and four edge maps are generated from 64x64 recognition window. Then a Feature vector is generated by dividing each edge map into 16 bins and number of edge flags in each bin are counted and 64 dimension feature vector is generated by concatenating 4 different histograms

System Architecture Function of this unit is to generate a 16 element Edge Histogram. The unit is composed of Functional Cache Memory for storing edge flag bits and Processing Element array for Edge Counting. The Functional Cache Memory includes four 64x65-SRAM banks and two Crossbar switches to be used for reordering of edge flag locations.

Functional Cache Memory Before scanning starts, we must store all the data of 64 columns of edge flag bits(256x64) in four SRAM banks. In each 64x65-SRAM bank, 64 columns are filled with edge bits and one column is left empty. Edge flags bits in every row are read out sequentially from the top row to bottom row and summed up to produce 16 element of histograms after 64 cycles.

Functional Cache Memory contd. When all 256 rows of data are read out, the recognition window must be shifted one pixel right. In generating a histogram from the vertical edge map, the basic operation is the summation of edge flag bits within vertical slots. However in case of +45 and -45 degrees edge maps, the addition of the diagonally adjacent edge flag bits is very complicated. To generate it, an arithmetic and shift algorithm has been developed.

Results The Chip was designed in a 0.18-um 5 metal CMOS technology and entire simulation was confirmed by Nano-Sim Simulation. The Architecture enables us to generate 3.9x10^7 feature vectors/second 100 MHz) which is 5x10^3 times faster than software processing using 2.16-GHz processor.

Comparison of Processing time for scanning 640x480 pixel image

Conclusion An image-feature-vector-generation VLSI has been developed aiming at building real-time recognition systems. By employing the functional cache memory architecture, seamless scanning of the recognition window over the entire image and generation of one feature vector/cycle have been accomplished. The system was designed for 256×256 size images, but it is easily extendible to larger size images by just increasing the number of SRAM banks in proportion to the height of the image. The chip was designed in a 0.18-μm 5-metal CMOS technology and the operation was confirmed by Nano sim simulation. If the chip is operated at 100 MHz, it is possible to scan a VGA-size image at a rate of 126 frames/sec, which is 20 times faster than the previous designs.