1. 1 Electronics Lab, Physics Dept., Aristotle Univ. of Thessaloniki, Greece 2 Micro2Gen Ltd., NCSR Demokritos, Greece 17th IEEE International Conference on Electronics, Circuits, and Systems ICECS 2010 – Athens - Greece

2.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 2

3.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 3

4.  Necessity of Edge Detection › First step in many computer vision algorithms › Identification of sharp discontinuities in an image  Why use the Canny algorithm › Good performance in images contaminated by noise  The need for Real-Time/High Throughput Implementation › Multiplication of camera resolutions in recent years › Real-time applications  The performance of modern FPGA devices › Powerful, efficient, availability of memory resources C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 4

5.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 5

6. 6 Smoothing Filter Calculation of gradient Localization Elimination of spurious responses

7.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 7

8.  Introduction of a 4-pixel parallel computation design  Pipelined architecture using on-chip BRAM memories for caching  Very efficient design with the same memory requirements as with a design without parallelism  In addition, complex arithmetical operations were substituted with shifts and additions/subtractions 8 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

9. 9  Exploitation of minimum buffering before starting the computation

10. 10 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  5 x 5 convolution › Introducing 4-pixel parallelism › Substitution of the multiplications and divisions with shifts additions and subtractions 25 pixels40 pixels

11. 11 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

12. 12 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  Exploitation of on-chip BRAMS › Use of one BRAM to accommodate one image line aligned in 4-pixel words › Each BRAM has a size of image width / 4 x 32 bits (grayscale)

13. 13 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  Start of calculations  As soon as the first 2 lines of the cache are filled › All non-existing lines and columns of pixels necessary for the calculations are considered to be black

14.  3 x 3 convolution › Introducing 4-pixel parallelism › Substitution of the multiplications and divisions with shifts additions and subtractions › Use of fixed point arithmetic 14 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 9 pixels18 pixels

15. 15 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  Start of calculations  As soon as the first line of the cache are filled › All non-existing lines and columns of pixels necessary for the calculations are considered to be black

16. 16 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  Same principles as in Sobel Gradient Calculation › Requires the 3 x 3 neighboring pixels 9 pixels18 pixels

17. 17 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab  Double Thresholding is a double comparator › No caching required for this stage  Hysterisis normally requires the 3 x 3 neighboring pixels › Reduced to 4 neighboring pixels › Second pass in the opposite direction

18. 18 C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab

19.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 19

20. C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 20 Synthesis Results GaussSobelNMSDb_ThresHysterisisTotalTotal(%) Frequency (MHz) Spartan 3E Slices 261310546493784420028%120.4 Spartan 6 Slices 241813916513612645602%201.4 Virtex 5 Slices 240913896484012445536%292.8  Synthesis results for 3 different FPGAs

21. C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 21 Image FileSizeTime (ms) lena 512x5120.66 HCLAChip 960x5401.31 Disc-brake 1280x9603.09  Timing results for Spartan-6

22.  Motivation  Canny Algorithm  Proposed Canny Implementation  Simulations – Results  Conclusions C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 22

23. C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 23  Real-time canny implementation › Parallel architecture with 4-pixel calculation › Increased throughput without increased need for memory resources › 240 frames per second achieved for 1Mpixel images on a Spartan-3E with 28% of the area › 580 frames per second on a Virtex-5 › 396 frames per second on a Spartan-6

24. The research activities that led to these results, were co-financed by Hellenic Funds and by the European Regional Development Fund (ERDF) under the Hellenic National Strategic Reference Framework (ESPA) 2007- 2013, according to Contract no. MICRO2-49-project LoC. C.-L. Sotiropoulou – Real-Time Canny FPGA Implementation – AUTH-eLab 24 Thank you very much for your attention!