7/14/ Design for Manufacturability Prof. Shiyan Hu Office: EERC 731

2 7/14/2015 Outline Manufacturability Basics CMP

3 7/14/2015 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

4 7/14/2015 Lithography systems

5 7/14/2015 Lithography Primer: Basics The famous Raleigh Equation: : Wavelength of the exposure system NA: Numerical Aperture (sine of the capture angle of the lens, and is a measure of the size of the lens system) k 1 : process dependent adjustment factor Exposure = the amount of light or other radiant energy received per unit area of sensitized material. Depth of Focus (DOF) = a deviation from a defined reference plane wherein the required resolution for photolithography is still achievable. Animation:

6 7/14/2015 Numerical Aperture NA=nsin   n=refractive index  for air, UB =1. Practical limit ≈ 0.93 NA increase  DOF decrease Immersion lithography ?  n>1 (e.g., water)

7 7/14/2015 k1 k1 is complex process depending on RET techniques, photoresist performance, etc Practical lower limit ≈ 0.25 Minimum resolvable dimension with 193nm steppers = 0.25*193/0.93 = 52nm Source:

8 7/14/2015 Mask versus Printing 0.25µ0.18µ 0.13µ 90-nm65-nm Layout Figures courtesy Synopsys Inc.

9 7/14/2015 Design Rules Explosion Number of design rules per process node

10 7/14/2015 CMP & Area Fill Area fill feature insertion Decreases local density variation Decreases the ILD thickness variation after CMP Post-CMP ILD thickness Features Area fill features wafer carrier silicon wafer polishing pad polishing table slurry feeder slurry Chemical-Mechanical Planarization (CMP) Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step

11 7/14/2015 Density Control Objectives Objective for Design = Min-Fill [Wong et al, DAC’00] minimize total amount of added fill subject to UB on window density variation

12 7/14/2015 Tiling and its Impact on PD The Tiling Problem: Given a layout and a CMP model, determine the location and amount of dummy features needed to achieve a planarity target, and then modify the layout accordingly.

13 7/14/2015 Tiling for ILD (Al Metallurgy)

14 7/14/2015 Tiling for Copper CMP

15 7/14/2015 Results from Tiling for STI - I Density and Post-CMP Topography Simulations for a DSP chip from Motorola: Original: max = 284A Tiled: max = 150A Topography Shape Density

16 7/14/2015 CMP Topography Variation CMP Topography variation –T =H MAX -H MIN.. Observations –Topography variation determines the depth of focus in lithography, an important factor of manufacturability. –Topography variation is determined by the feature density distribution of the circuit layout. –Feature density distribution varies with shuttle mask floorplans

17 7/14/2015 OPC/RET-Aware Routing [Huang, DAC’04; Mitra et al, DAC’05] OPC friendlyNot OPC friendly