Flip-Flops Section 4.3 Mano & Kime. D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

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Presentation transcript:

Flip-Flops Section 4.3 Mano & Kime

D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

D Flip-Flop X 0 Q 0 !Q 0 D NCK Q !Q Q !Q D !S !R S R CLK Pulse-narrowing circuit NCK X 0 Q 0 !Q 0 D CLK Q !Q

Pulse-Narrowing Circuit

D Flip-Flop CLK DQ !Q X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

D Flip-Flop CLK DQ !Q y CLK z pulse width setup time hold time propagation delay

Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches CLK xzy D E QD E Q CLK’ inputoutput x y z CLK’ CLK masterslave

SR Master-Slave Flip-Flop S R CLK Q !Q Q 0 !Q 0 Store Reset Set Disallowed X X 0 Q 0 !Q 0 Store

CLK K Q !Q J J-K Flip-Flop J K CLK Q !Q 0 0 Q 0 !Q Toggle X X 0 Q 0 !Q 0

Master-Slave J-K Flip-Flop

D-Type Positive Edge-Triggered Flip-Flop

Positive Edge-Triggered J-K Flip-Flop