1. Lecture No. 23 Sequential Logic

2. Digital Logic & Design Dr. Waseem Ikram Lecture No. 23

3. Recap Implementation of MUX Latch NAND based latch NOR based latch Logic symbols Timing diagrams

4. Latch Applications Switch ‘bounce’ (fig 1) Burglar Alarm (fig 1)

5. The output of a switch connected to Logic High

12. InputOutp ut CLKJKQ t+1 Pulse00QtQt 010 101 11

15. InputOutput Q t+1 00Invalid 011 100 11Clocked operation

22. Truth-Table of Positive and Negative Edge triggered D flip-flops InputOutput CLKDQ t+1 0XQtQt 1XQtQt ↑00 ↑11 InputOutput CLKDQ t+1 0XQtQt 1XQtQt ↓00 ↓11

25. Timing diagram of a Negative Edge triggered S-R flip-flop

26. Timing diagram of a Positive Edge triggered S-R flip-flop

27. InputOutput CLKSRQ t+1 0xxQtQt 1xxQtQt ↓00QtQt ↓010 ↓101 ↓11invalid

28. Truth-Table of Positive and Negative Edge triggered S-R flip-flops InputOutp ut CLKSRQ t+1 0XXQtQt 1XXQtQt ↑00QtQt ↑010 ↑101 ↑11inval id InputOutp ut CLKSRQ t+1 0xxQtQt 1xxQtQt ↓00QtQt ↓010 ↓101 ↓11inval id

31. Logic Symbol of Positive and Negative edge triggered S-R flip-flops

32. Timing diagram of the Negative clock edge detection circuit

33. Negative clock edge detection circuit

34. Timing diagram of the Positive clock edge detection circuit

35. Positive clock edge detection circuit

36. Gated D-latch used to store parallel data

37. Timing diagram of a gated D latch

38. Gated D Latch Q QD EN Logic Symbol of a Gated D Latch

39. Truth-Table of a gated D Latch InputOutput ENS (D)RQ t+1 0xXQtQt 100QtQt 1010 1101 111Invalid InputOutput ENDQ t+1 0xQtQt 100 111

40. Gated D Latch

41. Timing diagram of a gated S-R latch

42. InputOutput ENSRQ t+1 0xxQtQt 100QtQt 1010 1101 111invalid Truth-Table of a gated S-R Latch

43. Logic Symbol of a Gated S-R Latch

44. Gated S-R Latch

45. The switch connected through an S- R latch

47. The output of a switch connected to Logic High

48. Edge triggered flop-flop Gated S-R latch (fig 2) Logic symbol (fig 3) Function table (tab 1) Timing diagram (fig 4) Gated D latch (fig 5) Logic symbol (fig 6) Function table (tab 2) Timing diagram (fig 7) D-latch parallel data storage (fig 8)

49. Edge triggered flip-flop Edge detection circuit (fig 9) Logic symbol S-R flip-flop (fig 10) Function table (tab 3) Timing diagram (fig 11) Logic symbol D flip-flop (fig 12) Function table (tab 4) Timing diagram (fig 13)

50. Edge triggered J-K flip-flop J-K flip-flop (fig 14) Function table (tab 5) Logic symbol J-K flip-flop (fig 15) Timing diagram (fig 16)

51. Asynchronous Inputs J-K flip-flop with asynch. inputs (fig 8) Logic symbol asynch. J-K flip-flop (fig 9) Function table (tab 4) Timing diagram (fig 10)

52. Master-Slave flip-flop Master-Slave J-K flip-flop (fig 11) Function table (tab 5) Timing diagram (fig 12)

53. Flip-flop Operating Characteristics Propagation Delay (fig 13, 14, 15, 16) Set-up Time (fig 17) Hold Time (fig 18) Maximum clock frequency Pulse width Power Dissipation