1  1998 Morgan Kaufmann Publishers Chapter Four Arithmetic for Computers

2  1998 Morgan Kaufmann Publishers Arithmetic Where we've been: –Performance (seconds, cycles, instructions) –Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: –Implementing the Architecture 32 operation result a b ALU

3  1998 Morgan Kaufmann Publishers Some Questions How are negative numbers represented? What are the largest number that can be represented in a computer world? What happens if an operation creates a number bigger than can be represented? What about fractions and real numbers? Ultimately, how does hardware really add, subtract, multiply or divide number?

4  1998 Morgan Kaufmann Publishers Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers Binary numbers (base 2) decimal: n -1 Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Numbers

5  1998 Morgan Kaufmann Publishers Sign Magnitude: One's Complement Two's Complement 000 = = = = = = = = = = = = = = = = = = = = = = = = -1 Issues: balance, number of zeros, ease of operations Which one is best? Why? ASCII vs binary numbers (p212 example) Possible Representations

6  1998 Morgan Kaufmann Publishers 32 bit signed numbers: two = 0 ten two = + 1 ten two = + 2 ten two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = – 2,147,483,648 ten two = – 2,147,483,647 ten two = – 2,147,483,646 ten two = – 3 ten two = – 2 ten two = – 1 ten Binary to decimal conversion: two maxint minint MIPS

7  1998 Morgan Kaufmann Publishers Signed versus unsigned numbers It matters when doing comparison MIPS offers two versions of the set on less than comparison –slt, slti work with signed integers –sltu, sltiu work with unsigned integers

8  1998 Morgan Kaufmann Publishers Negating a two's complement number: invert all bits and add 1 –remember: “negate” and “invert” are quite different! –See example on page 216. (2, -2) Converting n bit numbers into numbers with more than n bits: –MIPS 16 bit immediate gets converted to 32 bits for arithmetic –copy the most significant bit (the sign bit) into the other bits > > –"sign extension" (lbu vs. lb) Binary-to-Hexadecimal conversion Two's Complement Operations

9  1998 Morgan Kaufmann Publishers Just like in grade school (carry/borrow 1s) Two's complement operations easy –subtraction using addition of negative numbers Overflow (result too large for finite computer word): –e.g., adding two n-bit numbers does not yield an n-bit number Addition & Subtraction

10  1998 Morgan Kaufmann Publishers No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: –overflow when adding two positives yields a negative –or, adding two negatives gives a positive –or, subtract a negative from a positive and get a negative –or, subtract a positive from a negative and get a positive Consider the operations A + B, and A – B –Can overflow occur if B is 0 ? –Can overflow occur if A is 0 ? Detecting Overflow

11  1998 Morgan Kaufmann Publishers An exception (interrupt) occurs –Control jumps to predefined address for exception –Interrupted address is saved for possible resumption Details based on software system / language –example: flight control vs. homework assignment Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons Effects of Overflow

12  1998 Morgan Kaufmann Publishers Logical Operations Shifts: move all the bits in a word to the left or right, filling the emptied bits with 0s. sll: shift left logical; srl :shift right logical Example: sll $t2, $s0, 8 shamt: shift amount and, andi or, ori

13  1998 Morgan Kaufmann Publishers Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true Show the truth table for these three functions. Show the Boolean equations for these three functions. Show an implementation consisting of inverters, AND, and OR gates. Review: Boolean Algebra & Gates (Appendix B)

14  1998 Morgan Kaufmann Publishers Let's build an ALU to support the andi and ori instructions –we'll just build a 1 bit ALU, and use 32 of them Possible Implementation (sum-of-products): b a operation result opabres An ALU (arithmetic logic unit)

15  1998 Morgan Kaufmann Publishers Selects one of the inputs to be the output, based on a control input S C A B 0 1 Review: The Multiplexor note: we call this a 2-input mux even though it has 3 inputs! C A B S

16  1998 Morgan Kaufmann Publishers Not easy to decide the “best” way to build something –Don't want too many inputs to a single gate –Don’t want to have to go through too many gates –for our purposes, ease of comprehension is important Let's look at a 1-bit ALU for addition: How could we build a 1-bit ALU for add, and, and or? How could we build a 32-bit ALU? Different Implementations c out = a b + a c in + b c in sum = a xor b xor c in

17  1998 Morgan Kaufmann Publishers Adder Hardware for the CarryOut Signal c out = a b + a c in + b c in

18  1998 Morgan Kaufmann Publishers How about the Sum bit? Leave as an exercise (page 329, 4.43)

19  1998 Morgan Kaufmann Publishers Building a 32 bit ALU

20  1998 Morgan Kaufmann Publishers Two's complement approach: just negate b and add. How do we negate? A very clever solution: What about subtraction (a – b) ?

21  1998 Morgan Kaufmann Publishers Need to support the set-on-less-than instruction (slt) –remember: slt is an arithmetic instruction –produces a 1 if rs < rt and 0 otherwise –use subtraction: (a-b) < 0 implies a < b Need to support test for equality (beq $t5, $t6, $t7) –use subtraction: (a-b) = 0 implies a = b Tailoring the ALU to the MIPS

Supporting slt Can we figure out the idea? (TOP) A 1-bit ALU that performs AND, OR, and addition on a and b or !b (BOTTOM) A 1-bit ALU for the most significant bit.

23  1998 Morgan Kaufmann Publishers 32 Bit ALU

24  1998 Morgan Kaufmann Publishers Test for equality Notice control lines: 000 = and 001 = or 010 = add 110 = subtract 111 = slt Note: zero is a 1 when the result is zero!

25  1998 Morgan Kaufmann Publishers Conclusion We can build an ALU to support the MIPS instruction set –key idea: use multiplexor to select the output we want –we can efficiently perform subtraction using two’s complement –we can replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware –all of the gates are always working –the speed of a gate is affected by the number of inputs to the gate –the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) Our primary focus: comprehension, however, –Clever changes to organization can improve performance (similar to using better algorithms in software) –we’ll look at two examples for addition and multiplication

26  1998 Morgan Kaufmann Publishers Is a 32-bit ALU as fast as a 1-bit ALU? Is there more than one way to do addition? –two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = Not feasible! Why? Problem: ripple carry adder is slow

27  1998 Morgan Kaufmann Publishers An approach in-between our two extremes Motivation: – If we didn't know the value of carry-in, what could we do? –When would we always generate a carry? g i = a i b i –When would we propagate the carry? p i = a i + b i Did we get rid of the ripple? c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 c 2 = c 3 = g 2 + p 2 c 2 c 3 = c 4 = g 3 + p 3 c 3 c 4 = Feasible! Why? Carry-lookahead adder

28  1998 Morgan Kaufmann Publishers Can’t build a 16 bit adder this way... (too big) Could use ripple carry of 4-bit CLA adders Better: use the CLA principle again! Use principle to build bigger adders

29  1998 Morgan Kaufmann Publishers Example Determine gi,pi,Pi and Gi for these two 16-bit numbers: a: b: Also, what is CarryOut15(or C4)?

30  1998 Morgan Kaufmann Publishers Speed of Ripple Carry vs. Carry Lookahead Take 16-bit adder as an example Ripple carry: the carry out signal takes two gate delays (Fig 4.13) 16x2 =32 Carry Lookahead C4 is the carry out bit of the msb, which takes two levels of logic to specify in terms of Pi and Gi Pi is specified in one level of logic using pi, Gi is specified in two levels of login using pi,gi, pi, gi are each one level of logic = 5 gate delays The Carry Lookahead method is 6.4 times faster than the ripple carry approach.