Fall 2006: Dec. 5 ELEC / Lecture 13 1 ELEC / (Fall 2006) Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL

Fall 2006: Dec. 5ELEC / Lecture 132 Examples of Power Saving and Energy Recovery Power saving by power transmission at high voltage: Power saving by power transmission at high voltage: 1000W transmitted at 100V, current I = 10A 1000W transmitted at 100V, current I = 10A If resistance of transmission circuit is 1Ω, then power loss = I 2 R = 100W If resistance of transmission circuit is 1Ω, then power loss = I 2 R = 100W Transmit at 1000V, current I = 1A, transmission loss = 1W Transmit at 1000V, current I = 1A, transmission loss = 1W Energy recovery from automobile brakes: Energy recovery from automobile brakes: Normal brake converts mechanical energy into heat Normal brake converts mechanical energy into heat Instead, the energy can be stored in a flywheel, or Instead, the energy can be stored in a flywheel, or Converted to electricity to charge a battery Converted to electricity to charge a battery

Fall 2006: Dec. 5ELEC / Lecture 133 Reexamine CMOS Gate i = Ve -t/RpC /R p i 2 R p V V 2 /R p C Time, t Power Most energy dissipated here VI = V 2 e -2t/RpC /R p 0 Energy dissipation = Area/2 = CV 2 /2 v(t) V 3R p C

Fall 2006: Dec. 5ELEC / Lecture 134 Charging with Constant Current i = K i 2 R p V(t) C Power 0 v(t) = Kt/C Time (T) to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/K Current, i = K = CV/T Output voltage, v(t) 0 V Time, t t=CV/K Kt/C Power = i 2 R p = C 2 V 2 R p /T 2 Energy dissipation = Power × T = (R p C/T) CV 2 C 2 V 2 R p /T 2

Fall 2006: Dec. 5ELEC / Lecture 135 Or, Charge in Steps i = Ve -t/RpC /2R p i 2 R p 0→V/2→V V 2 /4R p C Time, t Power V 2 e -2t/RpC /4R p 0 Energy = Area = CV 2 /8 v(t) V V/2 Total energy = CV 2 /8 + CV 2 /8 = CV 2 /4 3R p C6R p C

Fall 2006: Dec. 5ELEC / Lecture 136 Energy Dissipation of a Step T E = ∫V 2 e -2t/RpC /(N 2 R p ) dt 0 = [CV 2 /(2N 2 )] (1 – e -2T/RpC ) ≈ CV 2 /(2N 2 )for large T ≥ 3R p C Voltage step = V/N

Fall 2006: Dec. 5ELEC / Lecture 137 Charge in N Steps Supply voltage 0 → V/N → 2V/N → 3V/N →... NV/N Current, i(t) = Ve -t/RpC /NR p Power, i 2 (t)R p = V 2 e -2t/RpC /N 2 R p Energy = N CV 2 /2N 2 = CV 2 /2N→ 0 for N → ∞ Delay = N × 3R p C → ∞ for N → ∞

Fall 2006: Dec. 5ELEC / Lecture 138 References C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp , Dec W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp , Dec

Fall 2006: Dec. 5ELEC / Lecture 139 A Conventional Dynamic CMOS Inverter V C v(t) CK vin CK vin v(t) P E P E P E

Fall 2006: Dec. 5ELEC / Lecture 1310 Adiabatic Dynamic CMOS Inverter C v(t) CK vin A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp , March CK vin v(t) V0V0 V-Vf 0 Vf + P E P E

Fall 2006: Dec. 5ELEC / Lecture 1311 Cascaded Adiabatic Inverters CK1CK2CK1’CK2’ vin CK1 CK2 CK1’ CK2’ precharge input evaluate hold

Fall 2006: Dec. 5ELEC / Lecture 1312 Complex ADL Gate CK B A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp , March A C AB + C Vf < Vth

Fall 2006: Dec. 5ELEC / Lecture 1313 Quasi-Adiabatic Logic Two sets of diodes: One controls the charging path (D1) while the other (D2) controls the discharging path Two sets of diodes: One controls the charging path (D1) while the other (D2) controls the discharging path Supply lines have EVALUATE phase (  swings up) and HOLD phase (  swings low) Supply lines have EVALUATE phase (  swings up) and HOLD phase (  swings low) D1

Fall 2006: Dec. 5ELEC / Lecture 1314 Clocks EVAL. HOLD   0 0 V DD

Fall 2006: Dec. 5ELEC / Lecture 1315 Possible Cases: The circuit output node X is LOW and the pMOS tree is turned ON: X follows  as it swings to HIGH (EVALUATE phase) The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase) The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase) The circuit node X is HIGH and the nMOS tree is ON. X follows  down to LOW. Quasi-Adiabatic Logic Design

Fall 2006: Dec. 5ELEC / Lecture 1316 A Case Study K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis, Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.

Fall 2006: Dec. 5ELEC / Lecture 1317 Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Specifications Operating voltage: 2.5 V Operating voltage: 2.5 V Operating temperature: 25 o C Operating temperature: 25 o C Operating frequency: 10 MHz to 100 MHz Operating frequency: 10 MHz to 100 MHz Leakage current: 0.5 fAmps Leakage current: 0.5 fAmps Load capacitance: 6X F (15% activity) Load capacitance: 6X F (15% activity) Transistor Count: Transistor Count:

Fall 2006: Dec. 5ELEC / Lecture 1318 Technology Distribution Microprocessor has a mix of static CMOS and Quasi-adiabatic components Microprocessor has a mix of static CMOS and Quasi-adiabatic components ALU Adder-subtractor unit Barrel shifter unit Booth-multiplier unitALU Adder-subtractor unit Barrel shifter unit Booth-multiplier unit Control Units ARM controller unit Bus control unit Pipeline Units ID unit IF unit WB unit MEM unit Control Units ARM controller unit Bus control unit Pipeline Units ID unit IF unit WB unit MEM unit Quasi-AdiabaticStatic CMOS

Fall 2006: Dec. 5ELEC / Lecture 1319 Power Analysis DatapathComponent Power Consumption (mW) Frequency 25 MHz Power Consumption (mW) Frequency 100 MHz Quasi- adiabatic Static CMOS Power Saved Quasi- adiabatic Static CMOS Power Saved 32-bit Adder Subtracter % % 32-bit Barrel Shifter % % 32-bit Booth Multiplier % % Power Consumption (mW) Frequency 25 MHz Quasi- adiabatic Static CMOS Power Saved 60 mW 85 mW 40%

Fall 2006: Dec. 5ELEC / Lecture 1320 Power Analysis (Cont’d.)

Fall 2006: Dec. 5ELEC / Lecture 1321 Area Analysis DatapathComponent Area (mm 2 ) Quasi- adiabatic Static CMOS Area Increase 32-bit Adder Subtracter % 32-bit Barrel Shifter % 32-bit Booth Multiplier % Chip Area (mm 2 ) Quasi- adiabatic Static CMOS Area Increase %

Fall 2006: Dec. 5ELEC / Lecture 1322 Summary In principle, two types of adiabatic logic designs have been proposed: In principle, two types of adiabatic logic designs have been proposed: Fully-adiabatic Fully-adiabatic Adiabatic charging Adiabatic charging Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp , Dec W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp , Dec Quasi-adiabatic Quasi-adiabatic Adiabatic charging and discharging Adiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp , Feb Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp , Feb