Digital Logic Design Lecture 19. Announcements Homework 6 due Thursday 11/6 Recitation quiz on Monday, 11/10 – Will cover material from lectures 18,19,20.

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Presentation transcript:

Digital Logic Design Lecture 19

Announcements Homework 6 due Thursday 11/6 Recitation quiz on Monday, 11/10 – Will cover material from lectures 18,19,20 Change in Instructor Office Hours: – Tuesday 10am-11am – Thursday 11am-12pm

Agenda Last time: – Binary Adders and Subtracters (5.1, 5.1.1) – Carry Lookahead Adders (5.1.2, 5.1.3) This time: – Decimal Adders (5.2) – Comparators (5.3) – Decoders (5.4) – Encoders (5.5) – Multiplexers (5.6)

Decimal Adders 8421 weighted coding scheme or BCD Code Decimal DigitBCD Forbidden codes: 1010, 1011, 1100, 1101, 1110, 1111

Decimal Adder

Comparing Binary and BCD Sums Decimal SumK Same

Decimal Adder

A single-decade BCD Adder

Comparators Compare the magnitude of two binary numbers for the purpose of establishing whether one is greater than, equal to, or less than the other. A comparator makes use of a cascade connection of identical subnetworks similar to the case of the parallel adder.

Comparators

Decoder

Realization Logic Diagram Truth Table Symbol

Decoder Input combinations can be regarded as binary numbers with the consequences that the j-th output line is at logic-1 for j = 0, 1,.., 7 only when input combination j is applied.

Other types of Decoders

Logic Design Using Decoders

Minterms using OR Gates

Minterms using NOR Gates

Implementing a Decoder using NAND Logic Diagram Truth Table Symbol

Minterms using AND gates

Decoders with an Enable Input Logic Diagram Truth Table Symbol

Decoders with enable inputs When disabled, all outputs of the decoder can either be at logic-0 or logic-1. Enable input provides the decoder with additional flexibility. Idea: data is applied to the enable input. Process is known as demultiplexing. Enable inputs are useful when constructing larger decoders from smaller decoders. Data

Constructing Larger Decoders

Encoders

Priority Encoder