1. Combinational Logic By Taweesak Reungpeerakul
Chapter 3
Combinational Logic
By Taweesak Reungpeerakul

2. Contents Basic Combinational Logic Circuits
Implement SOP and POS using Basic Logic Gates
Universal Property of NAND and NOR
Combinational Logic using NAND and NOR
Operation with Pulse Waveforms
Digital System Application
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3. 3.1 Basic Combinational Logic Circuit
Inputs
A B C AB AC BC OUT AB AC BC
AB+AC+BC
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4. AND-OR-INV Logic Invert AND-OR in SOP  AND-OR-INV in POS
AB+AC+BC =(A+B)(A+C)(B+C)
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5. XOR
OUT = AB + AB
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6. XNOR
OUT = AB + AB = AB + AB
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7. 3.2 Implementing Combinational Logic
Ex#2: OUT = A(BC+DE)
Ex#1: OUT = ABC+DE
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8. From Truth Table Truth Table A B C OUT 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0
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9. Example Truth Table A B C OUT 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0
TableLogic Circuit  Karnaugh Map  Simplified Circuit
Truth Table
A B C OUT
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10. 2.3 Universal Property of NAND&NOR
INV, OR, AND, and NOR created by using NAND gates
INV
AND OR
NOR
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11. Universal Property of NOR
INV, OR, AND, and NAND created by using NOR gates
INV
AND OR
NAND
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12. 3.4 Combinational Logic using NAND & NOR
NAND; OUT = AB+CD
= AB+CD = (AB)(CD)
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13. Dual Symbols of NAND
Always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble.
ABC
AB+C
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14. Example: implemented by NAND
Ex1: ABC+DE
Ex2: ABC+D+E
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15. Combinational Logic using NOR
NOR; (A+B)(C+D)
= (A+B)(C+D) = (A+B)+(C+D)
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16. Dual Symbols
(A+B)+C
(A+B)C
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17. 3.5 Operation with Pulse Waveforms
Logic circuit  Timing diagram D C
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18. Develop logic circuit from waveforms
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19. Functions of Combinational Logic (Session 2)
Adders
Comparators
Decoders
Encoders
Code Converters
Multiplexers
Demultiplexers
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20. 3.6 Basic Adders Full Adder Half Adder A B Cin SUM Cout A B SUM Cout
Half Adder
A B SUM Cout
SUM = AB
Cout = AB
SUM = ABCin
Cout = AB+(AB)Cin
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21. Logic Symbol and Diagram
Half Adder
Full Adder
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22. Full Adder by 2 Half Adders
SUM = ABCin
Cout = AB+(AB)Cin
AB AB
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23. 3.7 Parallel Binary Adder A full adder is required for each A2A1
bit in the numbers.
A2A1
+ B2B1
S3S2S1
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Question: 4-bit numbers

24. 4-bit Parallel Adders An Bn Cn-1 Sn Cn 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
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25. IC:4-bit Parallel Adder
Example: 74LS83A (or 74LS283)
74LS83A
74LS283
Question: Show circuit diagram of
A+B by using 74LS83A. A =
and B =
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26. 3.8 Comparators Inequality Equality Comparing A and B: AB
IC: 74LS85
Equality
Comparing A and B: AB
If A=B, output = 0
If A≠B, output = 1
HIGH indicates equality: AB (XNOR)
A1A0 ? B1B0 A1 A0 A2 A3 B1 B0 B2 B3
Cascading inputs
COMP
A = B
A < B
A > B 3 A B
Outputs
Question: Show circuit diagram in order to compare two 8-bit numbers by using 74LS85.
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27. Two 74LS85 Cascaded Arrangement
Outputs A1 A0 A2 A3 B1 B0 B2 B3
COMP
A = B
A < B
A > B 3 A A5 A4 A6 A7 B5 B4 B6 B7
+5.0 V
LSBs
MSBs
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28. 74HC85 Truth Table
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29. 3.9 Decoders
A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. A0 A0 A1
OUT A1
OUT A2 A2 A3 A3
Active HIGH decoder for 0011
Active LOW decoder for 0011
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30. 4-to-16 Decoder A0 A1 A2 A3
CS1
CS2
IC: 74HC154
Question: Use 74HC154 to implement the logic in order to support a 5-bit number.
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31. BCD-to-Decimal Decoder
BCD-to-decimal decoders accept a binary coded decimal input and activate one of ten possible decimal digit indications.
IC: 74HC42
Question: Assume the inputs to the 74HC42 decoder are the sequence 0101, 0110, 0011, and Describe the output. A0
Answer: All lines are HIGH except for one active output, which is LOW. The active outputs are 5, 6, 3, and 2 in that order. A1 A2 A3
Question: Write truth table of output 0.
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32. BCD-to-7-Segment Decoder
IC: 74LS47
BCD Inputs (D-A)
7-segment Outputs (a -g)
Ripple Blanking Input
(RBI)
Blanking Input/Ripple Blanking Output (BI/RBO)
Lamp Test (LT)
Zero Suppression
VCC
BCD/7-seg
BI/RBO
BI/RBO
BCD inputs
Outputs to seven segment device LT LT
RBI
RBI
74LS47
GND
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33. Illustration of Leading Zero Suppression
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34. Illustration of Trailing Zero Suppression
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35. 3.10 Encoders
An encoder accepts an active logic level on one of its inputs representing a digit, such as a decimal or octal digits, and converts it to a coded output, such as BCD or binary.
IC: 74HC to-4 encoder (decimal-to-BCD)
IC: 74F148 8-to-3 encoder 1 A0 2 3 A1 4 5 A2 6 7 8 A3 9
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36. Example
Show how the decimal-to-BCD encoder converts the decimal number 3 into a BCD 0011. 1 1 1 A0 2 3 1 A1 4 5 A2 6 7 8 A3 9
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37. 74HC147
VCC
The 74HC147 is an example of an IC encoder. It has ten active-LOW inputs and converts the active input to an active-LOW BCD output.
This device offers additional flexibility with a priority encoder.
HPRI/BCD
Decimal input
BCD output
GND
74HC147
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38. A Simplified Keyboard Encoder
VCC
BCD complement of key press
The zero line is not needed by the encoder, but may be used by other circuits to detect a key press.
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39. 3.11 Code Converters BCD-to-BIN Conversion IC: 74184
BIN-to-BCD Conversion
IC: 74185
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40. Code Converters (cont.)
BIN-to-Gray
Gray-to-BIN
LSB
LSB G0 B0 B0 G0 B1 G1 G1 B1 B2 G2 B2 G2 B3 G3 G3 B3
MSB
MSB
Question: Show the conversion of binary 0111 to Gray and vice versa.
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41. 3.12 Multiplexers (MUX)
A multiplexer has several data-input lines and a single output line.
It also has data-select inputs, which permit digital data on any one of the inputs to be switched to the output line.
Another name is a data selector.
IC: 74HC157 Quad 2-input MUX
IC: 74HC151 8-input MUX S0
Data
select 1 S1 D0
Data
output D1
Data
inputs D2 D3
Question: Which data line is selected if S1S0 = 10?
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42. ICs
74HC157 Quad 2-input MUX
74HC151 8-input MUX
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43. 3.13 Demultiplexers (DEMUX)
74LS138
A DEMUX basically reverses the multiplexing function.
It takes data from one input line and distributes to one of output lines depending on the select lines.
Another name is a data distributor.
IC: 74LS138 8-output DEMUX
Data select lines 1
Data outputs
Enable
inputs
Question: Which data output is selected if A2A1A0 = 010?
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44. Example (DEMUX) Determine the outputs, given the inputs shown. A A A GA 1 A 2 G 1
Determine the outputs, given the inputs shown. G
LOW 2A G
LOW 2B Y Y
Data select lines 1 Y 2
Data outputs Y 3
Enable
inputs Y 4 Y 5 Y 6
74LS138 Y 7
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