Design Of Combinational Logic Circuits Dr. Costas Kyriacou and Dr. Konstantinos Tatas ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Design of combinational digital circuits Steps to design a combinational digital circuit: From the problem statement derive the truth table From the truth table derive the unsimplified logic expression Simplify the logic expression From the simplified expression draw the logic circuit Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic 1 only if the binary number formed at the input has more ones than zeros. ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Design of combinational digital circuits (Cont.) Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if the binary number formed at the input is between 2 and 9 (including). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Design of combinational digital circuits (Cont.) Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if the binary number formed by the inputs (AB) is greater or equal to the binary number formed by the inputs (CD). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Tutorial: Design a 4-input (A,B,C,D) digital circuit that will give at its output a binary number equal to the sum of the binary numbers formed by the inputs (AB) and (CD). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Tutorial: Design a 4-input (A,B,C,D) digital circuit that will give at the output: X a logic 1 if the binary number formed by the inputs (AB) is greater than (CD). Y a logic 1 if the binary number formed by the inputs (AB) is less than (CD). Z a logic 1 if the binary number formed by the inputs (AB) is equal to (CD). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Homework: Design a 4-input (A,B,C,D) digital circuit that will give at the output: X a logic 1 if in the binary number formed at the inputs there are more zeros than ones. Y a logic 1 if in the binary number formed at the inputs there are less zeros than ones. Z a logic 1 if in the binary number formed at the inputs there equal zeros and ones. ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Homework: Design a 4-input (A,B,C,D) digital circuit that will give at its output a binary number equal to the product of the binary numbers formed by the inputs (AB) and (CD). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Digital Logic For Computers (ACOE161) ACOE161 - Digital Logic for Computers - Frederick University Costas Kyriacou

ACOE161 - Digital Logic for Computers - Frederick University Don’t Care Conditions In many application it is known in advance that some of the input combinations will never occur. These combinations are marked as “Don’t Care Conditions” and are used as either zero’s or one’s so that the application is implemented with the most simplified circuit. Example: Simplify the logic expression X(A,B,C,D) with the don’t care conditions d(A,B,C,D). ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Don’t Care Conditions: Examples ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Homework: Design a digital circuit that has as input a 1-digit Binary Coded Decimal (BCD) number. The circuit must give at its output a binary number equal to the absolute value of (2M – 5), where M is the number formed at the input. ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

Digital Logic For Computers (ACOE161) ACOE161 - Digital Logic for Computers - Frederick University Costas Kyriacou

ACOE161 - Digital Logic for Computers - Frederick University

Digital Logic For Computers (ACOE161) ACOE161 - Digital Logic for Computers - Frederick University Costas Kyriacou

ACOE161 - Digital Logic for Computers - Frederick University Example Cell Library Cell Name Schematic Normalized Area Typical Input Load Input-to- Output Delay Basic Function Templates Inverter 1.00 0.04 1 0.012 3 SL 2NAND 1.25 0.05 0.014 2NOR 0.06 0.018 2-2 AOI 2.25 0.95 0.07 0.019 ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Mapping to NAND gates Assumptions: Gate loading and delay are ignored Cell library contains an inverter and n-input NAND gates, n = 2, 3, … An AND, OR, inverter schematic for the circuit is available The mapping is accomplished by: Replacing AND and OR symbols, Pushing inverters through circuit fan-out points, and Canceling inverter pairs ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

NAND Mapping Algorithm Replace ANDs and ORs: Repeat the following pair of actions until there is at most one inverter between : A circuit input or driving NAND gate output, and The attached NAND gate inputs. ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University NAND Mapping Example ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University Mapping to NOR gates Assumptions: Gate loading and delay are ignored Cell library contains an inverter and n-input NOR gates, n = 2, 3, … An AND, OR, inverter schematic for the circuit is available The mapping is accomplished by: Replacing AND and OR symbols, Pushing inverters through circuit fan-out points, and Canceling inverter pairs ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University NOR Mapping Algorithm Replace ANDs and ORs: Repeat the following pair of actions until there is at most one inverter between : A circuit input or driving NAND gate output, and The attached NAND gate inputs. ACOE161 ACOE161 - Digital Logic for Computers - Frederick University

ACOE161 - Digital Logic for Computers - Frederick University NOR Mapping Example ACOE161 ACOE161 - Digital Logic for Computers - Frederick University