Center for Embedded Computer Systems University of California, Irvine SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations Sumit Gupta Nikil Dutt Rajesh Gupta Alex Nicolau Supported by Semiconductor Research Corporation

High Level Synthesis M e m o r y ALU Control Data path d = e - fg = h + i If Node TF c x = a + b c = a < b j = d x g l = e + x x = a + b; c = a < b; if (c) then d = e – f; else g = h + i; j = d x g; l = e + x; Transform behavioral descriptions to RTL/gate level From C to CDFG to Architecture

Focus of this Paper Spark High-Level Synthesis Framework Spark High-Level Synthesis Framework Comprehensive synthesis framework Comprehensive synthesis framework Coordinated Coarse & Fine-Grain HLS and Compiler optimizations Coordinated Coarse & Fine-Grain HLS and Compiler optimizations C Input => RTL VHDL Output C Input => RTL VHDL Output Results in terms of Logic Synthesis Results (Area/Timing) Results in terms of Logic Synthesis Results (Area/Timing) Large, real-life applications: MPEG, Image Processing Large, real-life applications: MPEG, Image Processing Descriptions with complex and nested conditionals and loops Descriptions with complex and nested conditionals and loops Objectives: Objectives: Improve quality of HLS results by extracting a high degree of parallelization Improve quality of HLS results by extracting a high degree of parallelization Reduce impact of control constructs on QOR Reduce impact of control constructs on QOR Improve controllability of the HLS solutions Improve controllability of the HLS solutions

Recent Related Work Code motions in the presence of conditionals Code motions in the presence of conditionals Condition Vector List Scheduling [Wakabayashi 89] Condition Vector List Scheduling [Wakabayashi 89] Path Based Scheduling [Camposano 91] Path Based Scheduling [Camposano 91] Symbolic Scheduling [Radivojevic 96] Symbolic Scheduling [Radivojevic 96] WaveSched Scheduler [Lakshminarayana 98] WaveSched Scheduler [Lakshminarayana 98] Basic Block Control Graph Scheduling [Santos 99] Basic Block Control Graph Scheduling [Santos 99] Early work was on data-intensive DSP algorithms Early work was on data-intensive DSP algorithms Pipelining, Algorithmic transformations Pipelining, Algorithmic transformations

SPARK High Level Synthesis Framework C Input => RTL VHDL Output C Input => RTL VHDL Output VHDL => Logic Synthesis Results VHDL => Logic Synthesis Results Customizable Scheduler Customizable Scheduler Modular toolbox of transformations Modular toolbox of transformations Heuristics select transformations Heuristics select transformations

The Intermediate Representation Spark uses Hierarchical Task Graphs (HTG) Spark uses Hierarchical Task Graphs (HTG) Consists of hierarchy of basic blocks and HTG nodes Consists of hierarchy of basic blocks and HTG nodes 3 Types of HTG Nodes: Single, Compound, Loop 3 Types of HTG Nodes: Single, Compound, Loop Enables application of coarse and fine grain optimizations Enables application of coarse and fine grain optimizations Can regenerate C code Can regenerate C code Augmented by data dependency graphs Augmented by data dependency graphs

Loop HTG Node

Trailblazing: Code Motion Technique HTGs enable Hierarchical Operation Moves HTGs enable Hierarchical Operation Moves Does not visit each node in the graph Does not visit each node in the graph

Scheduling Heuristic BB 2BB 3 BB 1 BB 6BB 7 BB 5 BB 4 BB Speculate c b d + Across HTG Across HTG + a Get Available Ops Get Available Ops a, b, c, d a, b, c, d Determine Code Motions Required Determine Code Motions Required Assign Cost to each Operation Assign Cost to each Operation Cost is based on data dependency chain Cost is based on data dependency chain Schedule Op with lowest Cost Schedule Op with lowest Cost BB 0 BB 9 Speculate Across HTG

BB 2BB 3 BB 1 BB 6BB 7 BB 5 BB 4 BB c b + a BB 0 BB 9 + d Scheduling Heuristic BB 2BB 3 BB 1 BB 6BB 7 BB 5 BB 4 BB c b d + + Across HTG Conditional Speculation + a + d BB 0 BB 9 + d Speculate Across HTG

Experimentation Experiments for several transformations Experiments for several transformations Speculative Code Motions Speculative Code Motions Transformations applied during scheduling: Dynamic CSE Transformations applied during scheduling: Dynamic CSE We have used Spark to synthesize designs derived from several industrial designs We have used Spark to synthesize designs derived from several industrial designs MPEG-1 Prediction Block MPEG-1 Prediction Block GIMP Image Processing software GIMP Image Processing software Scheduling Results Scheduling Results Number of States in FSM Number of States in FSM Cycles on Longest Path through Design Cycles on Longest Path through Design VHDL: Logic Synthesis VHDL: Logic Synthesis Critical Path Length (ns) Critical Path Length (ns) Unit Area Unit Area

Code Motions: Logic Synthesis Results Within Basic Blocks & Across Hierar. Blocks + Speculation + Reverse Speculation & Early Condition Execution Condition Speculation Speculative Code Motions 50 % reduction in delay with 20 % Area increase 50 % reduction in delay with 20 % Area increase

CSE/Dynamic CSE Results All Code Motions Enabled + Only CSE + Only Dyanmic CSE + CSE & Dynamic CSE Dynamic CSE 30 % reduction in delay, 25 % reduction in Area 30 % reduction in delay, 25 % reduction in Area Speculative Code Motions + Dynamic CSE 75 % reduction in delay with No Area increase

Conclusions Comprehensive High-Level Synthesis framework Comprehensive High-Level Synthesis framework Behavioral C to RTL VHDL Behavioral C to RTL VHDL Hierarchical IR + Parallelizing Transformations Hierarchical IR + Parallelizing Transformations Toolbox of Transformations guided by Heuristics Toolbox of Transformations guided by Heuristics Basic compiler transformations: CSE, Copy Propagation Basic compiler transformations: CSE, Copy Propagation Platform for applying Coarse and Fine-grain Optimizations Platform for applying Coarse and Fine-grain Optimizations Experimentation with large industrial applications Experimentation with large industrial applications

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