SCIPP R&D on Linear Collider Tracking – Hardware and Simulation DOE Site Visit June Bruce Schumm Santa Cruz Institute for Particle Physics

Support Recently, ILC R&D has been supported at fluctuating levels by the DOE’s Linear Collider R&D (LCRD) program : We received $53,000 in regular funding, and have been told we will receive another $37,500 in supplemental funding : We have been told to expect $51,000. We might also expect some additional supplemental funding. Virtually all funding has been used to support the hardware project.

Faculty/Senior Vitaliy Fadeyev Alex Grillo Bruce Schumm Post-Docs Jurgen Kroseberg Lei Wang Undergrads Greg Horn Luke Kelley Ian Horn Sean Crosby The SCIPP/UCSC SiLC/SiD GROUP (Harwdare R&D Participants) Lead Engineer: Ned Spencer Technical Staff: Max Wilder, Forest Martinez-McKinney All participants are mostly working on other things (BaBar, ATLAS, biophysics, Undergraduate major…) Students are undergraduate physics majors at UCSC

FOCUS AND MILESTONES Goal: To develop readout generically suited to any ILC application (long or short strips, central or forward layers) Current work focused on long ladders (more challenging!): Front-end electronics for long (~1 meter) ladders Exploration of sensor requirements for long ladders Demonstration (test-beam) of < 10  m resolution mid-2008 After long-ladder proof-of-principle, will re-optimize (modest changes) for short-ladder, fast-rate application We also hope to play an increasing role in overall system development (grounding/shielding, data transmission, module design and testing) as we have on ATLAS and GLAST

BRIEF SUMMARY OF STATUS Testing of 8-channel (LSTFE-1) prototype fairly advanced: Reproducible operation (4 operating boards) Most features working, with needed refinements understood A number of “subtleties” (e.g. channel matching, environmental sensitivity) under control Starting to make progress on fundamental issues confronting long-ladder/high-resolution limit. Design of 128-channel prototype (LSTFE-2) well underway (July submission) Now for the details…

Pulse Development Simulation Long Shaping-Time Limit: strip sees signal if and only if hole is collected onto strip (no electrostatic coupling to neighboring strips) Include: Landau deposition (SSSimSide; Gerry Lynch LBNL), variable geometry, Lorentz angle, carrier diffusion, electronic noise and digitization effects Christian Flacco & Michael Young (Grads); John Mikelich and Luke Kelley (Undergrads)

1-3  s shaping time (LSTFE-I is ~1.2  s); analog measurement is Time-Over-Threshold Process: TSMC 0.25  m CMOS The LSTFE ASIC

1/4 mip 1 mip 128 mip Operating point threshold Readout threshold High gain advantageous for overall performance (channel matching)

Simulated Resolution for 167 cm Ladder Detector Noise: Capacitive contribution; from SPICE simulation normalized to bench tests with GLAST electronics Analog Measurement: Provided by time-over- threshold; lookup table provides conversions back into analog pulse height (as for actual data) RMS Gaussian Fit Detector Resolution (units of 10  m) Lower (read) threshold in fraction of min-i (High threshold is at 0.29 times min-i)

DIGITAL ARCHITECTURE: FPGA DEVELOPMENT Digital logic under development on FPGA (Wang, Kroseberg), will be included on front-end ASIC after performance verified on test bench and in test beam.

FIFO (Leading and trailing transitions) Low Comparator Leading-Edge-Enable Domain Proposed LSTFE Back-End Architecture Clock Period  = 400 nsec Event Time 8:1 Multi- plexing (  clock = 50 ns)

Note on LSTFE Digital Architecture Use of time-over-threshold (vs. analog-to- digital conversion) permits real-time storage of pulse-height information.  No concern about buffering  LSTFE system can operate in arbitrarily high-rate environment; is ideal for (short ladder) forward tracking systems as well as long-ladder central tracking applications.

FPGA-based control and data- acquisition system INITIAL RESULTS LSTFE chip mounted on readout board

Comparator S Curves Vary threshold for given input charge Read out system with FPG-based DAQ Get 1-erf(threshold) with 50% point giving response, and width giving noise Stable operation to V thresh ~ 5% of min-I Q in = 0.5 fC Q in = 3.0 fC Q in = 2.5 fC Q in = 2.0 fC Q in = 1.5 fC Q in = 1.0 fC Hi/Lo comparators function independently

Noise vs. Capacitance (at  shape = 1.2  s) Measured dependence is roughly (noise in equivalent electrons)  noise = *C with C in pF. Experience at 0.5  m had suggested that model noise parameters needed to be boosted by 20% or so; these results suggest 0.25  m model parameters are accurate  Noise performance somewhat better than anticipated. Observed Expected 1 meter EQUIVALENT CAPACITANCE STUDY

Preamp Response Power Control Shaper Response Power Cycling (with Small Injected Current for now) It is essential to turn off chip for the 99% of the time that the beam is not there  Must be able to turn chip back on in 1 millisecond! Solution in hand to maintain bias levels in “off” state with low-power feedback; will eliminate need for external trickle current

LONG LADDER CONSTRUCTION

Measured Noise vs. Sum of Estimated Contributions 72 cm Ladder Estimated Johnson noise for actual 65  m strip (part of estimate) Projected Johnson noise for 20  m strip (not part of estimate) Measured noise Sum of estimates 143 cm Ladder Noise calculation assuming 20  m strip width (actual is 60  m)

Strip Noise Idea: “Center Tapping” – half the capacitance, half the resistance? Result: no significant change in measured noise However, sensors have 237  m pitch  Currently characterizing CDF L00 sensors Measured noise Expected noise, assuming 75% reduction in strip noise

Summary/Outlook [Hardware effort] Development of chip in relatively advanced stage LSTFE-2 to be submitted this summer; test beam fall or winter Version optimized for short strips shortly thereafter Will soon open discussion with LBNL and/or UCSC engineering to incorporate digital architecture on back end Final test-beam run in late 2009

Tracking Validation Studies Non-prompt tracks with SiD Tracking Simulation Studies at UC Santa Cruz

Tracking Performance Package Package is C++/ROOT written by Chris Meyer (UCSC physics major) Reads in platform-independent flat file with specific format (output by JAS, …) Flat file includes all relevant particles (MC) and tracks, with two-way MC Truth cross-referencing, and track/particle attributes Also reads in error-matrix information in cos  /p grid (e.g. from LCDTRK)

Efficiency vs.  500 GeV uds pT > 0.75 GeV pT > 5.0 GeV Some examples…  = angle between jet axis and track

“Tri-Plots” (fitting validation)

II. Non-Prompt Tracks with the SiD About 5% of tracks originate outside the 2 nd layer of the VXD. Is the SiD able to reconstruct these?

People and Contributions I Tim Nelson (SLAC) AxialBarrelTracker (Snowmass ’05) finds tracks using only the five central tracking layers Begins with three track “seed” from outer layers and works inwards Designed to find prompt tracks if VXD disabled

People and Contributions II Tyler Rice (UCSC Physics Major) Optimize AxialBarrelTracker for non-prompt tracks Benchmark and enhance performance Lori Stevens (UCSC Physics Major) Introduce z-segmentation algorithm into AxialBarrelTracker Study performance vs. z segmentation

“Found”: associated with a track, with at most one hit coming from a different particle. “Fake”: Any non-associated track with p t >0.75 and DCA < 100mm. ParticlesFakes Found 5 Hits131(43%) 1 Found 4 Hits100(33%) 270 Not Found 73(24%) AxialBarrelTracker Effieciency Studies Out of 304 “findable” particles in Z 0  bb events Find 43% of particles Four-hit tracks seem difficult

Sources of Inefficiency Restrict to particles that hit all five layers: 166 Findable MC Particles (304 before requirement) 113 Found with 5 hits (68% vs. 43%) 25 Found with 4 hits (15% vs. 33%) 28 Missed (17% vs. 24%) Also require all three “seed” hits to be from same particle: 144 Found with 5 hits (87% vs. 43%) 15 Found with 4 hits (9% vs. 33%) 7 Missed (4% vs. 24%)

Improving AxialBarrelTracker Efficiency For the vast majority of particles, all hits are within  /2 of one another in azimuth (  ). Make this restriction… With Azimuthal Restriction % of MCPs Without Azimuthal Restriction % of MCPs # of MCPs %304100% Found with 5 hits 14548%13143% Found with 4 hits 11237%10033% Missed 4715%7324% Fake (4 hit / 5 hit) 157 / 1270 /1 Some improvements in efficiency and reduction of fakes…

Note: Not actual spacing between modules Hit 1 Hit 2 Possible modules for following hits Z Segmentation Can we use z-segmentation to further clean up seeds and eliminate fake tracks? Can we make 4-hit tracks usable? For now, apply only to three-hit seeds…

AxialBarrelTracker Effieciency Two halves (original) 30cm segments 10cm segments 5cm segments 1cm segments # MCPs Found with 5 hits Found with 4 hits Missed hit fake Application of segment consistency to seeds provides improvement, but only for lengths less than 10cm

AxialBarrelTracker Effieciency

Summary/Outlook [Simulation effort] UCSC Undergraduates making important contribution to development of SiD detector. Are part of core simulation collaboration with SLAC, FNAL, Kansas State and Brown. One student (Lori Stevens) awarded SLAC’s Pope Fellowship for this summer; will work under Norman Graf. Rice and Myers will be supported this summer with LCRD funds. Strategizing meeting tomorrow at noon (SLAC/UCSC) to lay out summer plans.

RANDOM BACK-UP SLIDES

TIME-OVER-THRESHOLD READOUT SUMMARY The LSTFE readout system is: Universally applicable (long strips, short strips, central, forward, SiD, LDC, GLD, 4 th …) Rigorously optimized for ILC tracking Relative simple (reliability, yield) In a relatively advanced stage of development Is now being used as an instrument to understand fundamental principles of long ladder operation, particularly for narrow strips (CDF Layer00 sensors available, being qualified)

Silicon Microstrip Readout R&D Initial Motivation Exploit long shaping time (low noise) and power cycling to: Remove electronics and cabling from active area (long ladders) Eliminate need for active cooling SiD Tracker

c The Gossamer Tracker Ideas: Low noise readout  Long ladders  substantially limit electronics readout and support Thin inner detector layers Exploit duty cycle  eliminate need for active cooling Competitive with gaseous tracking over full range of momentum (also: forward region) Alternative: shorter ladders, but better point resolution

The LSTFE approach would be well suited to use in short-strip applications, and would offer several potential advantages relative to other approaches Optimized for LC tracking (less complex) More efficient data flow No need for buffering Would require development of 2000 channel chip w/ bump bonding (should be solved by KPiX development)

LSTFE-2 DESIGN LSTFE-1 gain rolls off at ~10 mip; are instituting log-amp design (50 mip dynamic range) Power cycling sol’n that cancels (on-chip) leakage currents Improved environmental isolation Additional amplification stage (noise, shaping time, matching Improved control of return-to-baseline for < 4 mip signals Multi-channel (64? 128? 256?) w/ 8:1 multiplexing of output Must still establish pad geometry (sensor choice!)

Note About LSTFE Shaping Time Original target:  shape = 3  sec, with some controlled variability (“ISHAPR”)  Appropriate for long (2m) ladders In actuality,  shape ~ 1.5  sec; tests are done at 1.2  sec, closer to optimum for SLAC short- ladder approach Difference between target and actual shaping time understood in terms of simulation (full layout) LSTFE-2 will have ~3  sec shaping time

Power Cycling Idea: Latch operating bias points and isolate chip from outside world. Per-channel power consumption reduces from ~0.5 mW to ~5  W. Restoration to operating point should take ~ 1 msec. Current status: Internal leakage (protection diodes + ?)degrades latched operating point Restoration takes ~40 msec (x5 power savings) Injection of small current (< 1 nA) to counter leakage allows for 1 msec restoration. Future (LSTFE-2) Low-current feedback will maintain bias points; solution already incorporated in LSTFE-2 design

LONG LADDER EXPERIENCE A current focus of SCIPP activity Using GLAST “cut-off” (8 channel) sensors; 237  m pitch with 65  m strip width Have now studied modules of varying length, between 9cm and 143cm. Measure inputs to estimate noise sources other than detector capacitance: Leakage current1.0 nA/cm Strip resistance3.1  /cm Bias resistance35 M  per sensor All of these should be considered in module design! Strip resistance for fine pitch could be an issue  are doing dedicated studies and considering options  feedback to detector/module design.

Simulation Result: S/N for 167 cm Ladder (capacitive noise only) Simulation suggests that long-ladder operation is feasible

Timing Resolution Study (50 pF Load) Nominal expectation: where  = 1.2  s is the shaping time,  = 8.8 is the applied threshold in units of rms noise, and SNR = 28. This yields an expectation of  t ~ 60 ns (expected)  t was measured at a series of input charges, which were averaged together with weights from a Landau distributions, yielding  t ~ 50 ns (measured)

Number of hits on track Track Momentum “Good” “Other” “Knock-on” (less than 10 MeV) “Looper” Total hits: % Good hits: % Looper hits: % Knock-on hits: % Other hits: % Total tracks: % Good tracks:4456.6% Looper tracks:4596.8% Knock-on tracks: % Other tracks: % What’s left after “finding” (cheating!) prompt tracks?

DIGITAL ARCHITECTURE SIMULATION ModelSim package permits realistic simulation of FPGA code (signal propagation not yet simulated) Simulate detector background (innermost SiD layer) and noise rates for 500 GeV running, as a function of read- out threshold. Per 128 channel chip ~ 7 kbit per spill  35 kbit/second For entire SiD tracker ~ GHz data rate, dep- ending on ladder length (x100 data rate suppression) Nominal Readout Threshold

Channel-to-Channel Matching Offset: 10 mV rms Gain: 150 mV/fC <1% rms Occupancy threshold of 1.2 fC (1875 e - )  180 mV ± 2 mV (20 e - ) from gain variation ± 10 mV (100 e - ) from offset variation