1. SCIPP R&D on the International Linear Collider Detector DOE Site Visit June 8, 2006 Presenter: Bruce Schumm

2. R&D Activity is increasing, with studies now on a number of fronts:  Physics/machine studies for e - e - running (see Heusch)  Billior-based calculation of tracking errors  Detector resolution standards from physics simulation  Reconstruction capabilities of all-silicon tracking  Hardware proof-of-principle of low-noise silicon strip readout Summary of Activities

3. Current Involvements (all part time) 4 senior physicists 1 post-doc (looking for a second) 8 undergraduate students (major contribution) 1 engineer and 2 technical staff 1 bored spouse of a Silicon Valley engineer. Leadership Roles Heusch is member of International Cooperation Committee Schumm is lead convener of North American Tracking Working Group

4. Detector Resolution Standards from Selectron Production Participants: Senior Physicist Bruce Schumm Undergraduate Thesis Students Sharon Gerbode, Heath Holguin, Troy Lau *, Paul Moser, Adam Perlstein, Joseph Rose, Matthew Vegas Community Member (on hold before Grad School) Ayelet Lorberbaum * Recipient of two Undergraduate Research Awards; grad school at U. Michigan.

5. Motivation To explore the effects of limited detector resolution on our ability to measure SUSY parameters in the forward region. SiD Tracker

6. SPS1A at 1 TeV Selectrons vs. cos(  ) Electrons vs. cos(  ) Roughly ½ of statistics above |cos(  )| of 0.8, but…

7. The spectrum is weighted towards higher energy at high |cos(  )|, so there’s more information in the forward region than one might expect.

8. Determine the selectron mass accuracy in both the central (0 < |cos  | <.8) and full (0 < |cos  | < 1) region

9. Ongoing work: Fitting simulaneously for selectron and gaugino (  0 ) masses at E cm = 500 GeV This is an ILC Physics benchmark process (Schumm, Vegas)

10. Simulation of SiD Tracking System (and SiD variants) Participants: Senior Physicist Bruce Schumm Graduate Student Michael Young (Master’s August 2005) Undergraduate Students / Other Tyler Rice, Lori Stevens, Eric Wallace, Ayelet Lorberbaum

11. Three areas of work: Fast MC Simulation Billior-based LCDTRK.f (B. Schumm) provides covariance matrices for fast MC simulation and resolution plots. SiD Tracking Capabilities Explore tracking performance of SiD tracker and variants Microstrip Pulse Development Simulation Provides simulation of pulse development and amplification for designing and detector layout Simulation of SiD Tracking System, continued

12. LCDTRK.f comparison of SiD options with TESLA (LDC) design, from Snowmass 2005

13. Pattern Recognition Capabilities of an All- Silicon Central Tracker Can one do pattern recognition with only five central tracking layers? Might more layers improve performance to an extent that justifies the extra material? SiD Tracker Current code: “VXDBasedReco” Nick Sinev, Oregon

14. EFFICIENCIES FOR QQBAR EVENTS Doesn’t look that spectacular; what might be going on here?

15. Of course! The requirement of a VXD stub means that you miss anything that originates beyond r ~ 3cm. This is about 5% of all tracks. With current “VXDBasedReco” algorithm, we won’t get the ~5% of tracks that originate beyond 2cm.

16. Outside-in Tracking (Eric Wallace) Essential tool for SiD tracker optimization. Circle-fit tracker (Tim Nelson, SLAC) developed at Snowmass, makes use only of central tracker information Eric has merged this with VXDBasedReco to provide efficiency for non-prompt tracks All remaining tracks Found Not found Radial Origin (mm) Remaining tracks found with ~80% efficiency

17. CURVATURE ERROR vs. CURVATURE Standard (Original) Code Michael Young, Eric Wallace

18. Ongoing Track Reconstruction Work Primary focus of new crop of undergrad thesis students (plus Ayelet Lorberbaum) Expand Eric’s work to get polished combined-algorithm tracking code Explore other tracking algorithms (GARFIELD calorimeter- stub extender [Kansas State], Kalman filter code [SLAC, Colorado]) Begin to optimize SiD geometry (number of layers, layer spacing, tracker radius)

19. Faculty/Senior Vitaliy Fadeyev Alex Grillo Bruce Schumm Abe Seiden Post-Docs Jurgen Kroseberg [Active Search] Students Greg Horn Glenn Gray Bryan Matsuo (Comp.Sci.) The SCIPP/UCSC ILC HARDWARE GROUP Lead Engineer: Ned Spencer Technical Staff: Max Wilder, Forest Martinez-McKinney Primary Goal: Overall proof-of-principle in 2008 test beam run

20. Silicon Microstrip Readout R&D Initial Motivation Exploit long shaping time (low noise) and power cycling to: Remove electronics and cabling from active area (long ladders) Eliminate need for active cooling SiD Tracker

21. The Gossamer Tracker Ideas: Low noise readout  Long ladders  substantially limit electronics readout and support Thin inner detector layers Exploit duty cycle  eliminate need for active cooling Competitive with gaseous tracking over full range of momentum (also: forward region) Alternative: shorter ladders, but better point resolution

22. Pulse Development Simulation Long Shaping-Time Limit: strip sees signal if and only if hole is collected onto strip (no electrostatic coupling to neighboring strips) Include: Landau deposition (SSSimSide; Gerry Lynch LBNL), variable geometry, Lorentz angle, carrier diffusion, electronic noise and digitization effects Christian Flacco & Michael Young (Grads); John Mikelich (Undergrad)

23. Result: S/N for 167cm Ladder Simulation suggests that long-ladder operation is feasible

24. 3  s shaping time; analog readout it Time-Over-Thres- hold with 400 nsec clock Process: TSMC 0.25  m CMOS The LSTFE-2 ASIC

25. 1/4 mip 1 mip 128 mip Operating point threshold Readout threshold

26. Electronics Simulation Detector Noise: From SPICE simulation, normalized to bench tests with GLAST electronics Analog Measurement: Employs time-over- threshold with variable clock speed; lookup table provides conversions back into analog pulse height (as for actual data) RMS Gaussian Fit Detector Resolution (units of 10  m) Essential tool for design of front-end ASIC

27. FPGA-based control and data- acquisition system INITIAL RESULTS LSTFE-2 chip mounted on readout board

28. 0.46 fC 0.80 fC 1.73 fC 2.04 fC 1.42 fC1.11 fC Comparator S Curves Vary threshold for given input charge Read out system with FPG-based DAQ Get 1-erf(threshold) with 50% point giving response, and width giving noise Data & Plots: Greg Horn

29. Current Results Gain and Noise (Load = 150 pF, or about a 115 cm detector) Result: ~5300 electrons noise Expectation: ~1400 electrons noise Picoprobe studies isolate problem to shaper stage Power Cycling Switch-on time 20-40 msec gives 10-20% duty cycle (want 1-2%) Development of next version of LSTFE chip underway Data & Plots: Greg Horn

30. DIGITAL ARCHITECTURE: FPGA DEVELOPMENT Digital logic should perform basic zero suppression (intrinsic data rate for entire tracker would be approximately 50 GHz), but must retain nearest-neighbor information for accurate centroid.

31. FIFO (Leading and trailing transitions) Low Comparator Leading-Edge-Enable Domain Proposed LSTFE Back-End Architecture Clock Period  = 400 nsec Event Time 8:1 Multi- plexing (  clock = 50 ns)

32. DIGITAL ARCHITECTURE VERIFICATION ModelSim package permits realistic simulation of FPGA code (signal propagation not yet simulated) Simulate detector background and noise rates for 500 GeV running, as a function of read- out threshold. Per 128 channel chip ~ 7 kbit per spill  35 kbit/second For entire long shaping-time tracker ~ 0.5 GHz data rate (x100 data rate suppression) Nominal Readout Threshold

33. LONG LADDER CONSTRUCTION

34. OVERALL SUMMARY Linear Collider R&D at SCIPP is: Directly benefiting from SCIPP expertise Focused on central issues for the ILC that are applicable to any detector scenario On track for testbeam proof-of-principle in 2008 Supporting leadership roles (international cooperation, oversight of tracking RD) Providing key educational opportunities, undergrad through postdoc, with a good placement record