FPGA Defect Tolerance: Impact of Granularity Anthony YuGuy Lemieux December 14, 2005

2Field-Programmable Technology (FPT) '05 Outline Introduction and motivation Introduction and motivation Previous works Previous works New architectures New architectures Coarse-grain redundancy (CGR) Coarse-grain redundancy (CGR) Fine-grain redundancy (FGR) Fine-grain redundancy (FGR) Experimentation Results Experimentation Results Conclusions Conclusions

3Field-Programmable Technology (FPT) '05 Introduction and Motivation Scaling introduces new types of defects Scaling introduces new types of defects Smaller feature sizes susceptible to smaller defects Smaller feature sizes susceptible to smaller defects Expected results Expected results Defects per chip increases Defects per chip increases Chip yield declines Chip yield declines FPGAs are mostly interconnect FPGAs are mostly interconnect FPGAs must tolerate multiple interconnect defects to improve yield (and $$$) FPGAs must tolerate multiple interconnect defects to improve yield (and $$$)

4Field-Programmable Technology (FPT) '05 General Defect Tolerant Techniques Defect-tolerant techniques minimize impact (cost) of manufacturing defects Defect-tolerant techniques minimize impact (cost) of manufacturing defects FPGA defect-tolerance can be loosely categorized into three classes: FPGA defect-tolerance can be loosely categorized into three classes: Software Redundancy – use CAD tools to map around the defects Software Redundancy – use CAD tools to map around the defects Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR) Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)

5Field-Programmable Technology (FPT) '05 Previous work – 1 – Xilinx Xilinx’s Defect-Tolerant Approach Xilinx’s Defect-Tolerant Approach Customer (knowingly) purchases “less that perfect” parts Customer (knowingly) purchases “less that perfect” parts Customer gives Xilinx configuration bitstream Customer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstream Xilinx tests FPGA devices against bitstream Sells FPGA parts that “appear” perfect Sells FPGA parts that “appear” perfect Defects avoid the bitstream Defects avoid the bitstream Limitation: Limitation: Chips work only with given bitstream – no changes! Chips work only with given bitstream – no changes!

6Field-Programmable Technology (FPT) '05 Previous work – 2 – Altera Altera’s Defect-Tolerant Approach Altera’s Defect-Tolerant Approach Customer purchases “seemingly perfect” parts Customer purchases “seemingly perfect” parts Make defective resources inaccessible to user Make defective resources inaccessible to user Coarse-grain architecture Coarse-grain architecture Spare row and column in array (like memories) Spare row and column in array (like memories) Defective row/column must be bypassed Defective row/column must be bypassed Use the spare row/column instead Use the spare row/column instead Limitation: Limitation: Does not scale well (multiple defects) Does not scale well (multiple defects)

7Field-Programmable Technology (FPT) '05 Objective Problem Problem FPGA yield is on decline because of aggressive technology scaling FPGA yield is on decline because of aggressive technology scaling Proposed Solutions Proposed Solutions Defect-tolerance through redundancy Defect-tolerance through redundancy Important Objectives Important Objectives Interconnect defects important (dominates area) Interconnect defects important (dominates area) Tolerate multiple defects (future trend) Tolerate multiple defects (future trend) Preserve timing (no timing re-verification) Preserve timing (no timing re-verification) Fast correction time (production use) Fast correction time (production use) Understand the factors that influence yield Understand the factors that influence yield

Background

9Field-Programmable Technology (FPT) '05 Island-style FPGA

10Field-Programmable Technology (FPT) '05 Directional Switch Block

11Field-Programmable Technology (FPT) '05 Directional Switch Block

Course-grain Redundancy (CGR)

13Field-Programmable Technology (FPT) '05 Coarse-grain Redundancy (CGR)

14Field-Programmable Technology (FPT) '05 So…what’s wrong with it?

15Field-Programmable Technology (FPT) '05 Improving yield for CGR – Adding Multiple Global Spares Add multiple global spare to traditional CGR Add multiple global spare to traditional CGR Global spares can be used to repair any defective row/column in the array Global spares can be used to repair any defective row/column in the array Wire extensions are now longer Wire extensions are now longer

16Field-Programmable Technology (FPT) '05 Yield Impact of Multiple Global Spares

17Field-Programmable Technology (FPT) '05 Increasing Area+Delay Overhead 1 GLOBAL SPARE 2 GLOBAL SPARES 4 GLOBAL SPARES MAY BE IMPRACTICAL !!! NO SPARES MORE SPARES  MORE MUX OVERHEAD IN EVERY SWITCH ELEMENT

18Field-Programmable Technology (FPT) '05 Improving yield for CGR – Adding Multiple Local Spares Divide FPGA into subdivisions Divide FPGA into subdivisions Each subdivision has local spare(s) Each subdivision has local spare(s) Distributes spares across chip Distributes spares across chip Reduces mux area overhead (of Global scheme) Reduces mux area overhead (of Global scheme) Limitation: Limitation: Spare(s) can only repair defect within the subdivision Spare(s) can only repair defect within the subdivision

19Field-Programmable Technology (FPT) '05 Yield Impact of Multiple Local Spares (not as good as Global with same # spares)

Fine-grain Redundancy (FGR)

21Field-Programmable Technology (FPT) '05 Fine-grain Redundancy (FGR) – Defect Avoidance by Shifting

22Field-Programmable Technology (FPT) '05 Defect-tolerant Switch Block

23Field-Programmable Technology (FPT) '05 Switch Implementation Options Several detailed implementations are possible Trade off area / delay / yield(repairability)

24Field-Programmable Technology (FPT) '05 Minimum Fault-free Radius (MFFR)

25Field-Programmable Technology (FPT) '05 Experimentation Results Switch implementation Switch implementation Array size Array size Wire length Wire length Area Area Summary Summary

26Field-Programmable Technology (FPT) '05 Switch Implementation * Assumes all bridging defects

27Field-Programmable Technology (FPT) '05 Fixed Array Size (32x32) – Global Sparing

28Field-Programmable Technology (FPT) '05 Fixed Array Size (32x32) – Local Sparing

29Field-Programmable Technology (FPT) '05 Increasing Array Size

30Field-Programmable Technology (FPT) '05 Yield for Varying Wire Length

31Field-Programmable Technology (FPT) '05 Estimated Area overhead at equal yield (80%) * CGR-G1 can only tolerate 1-2 defects

32Field-Programmable Technology (FPT) '05 Limitations of Study & Architectures Logic and power/ground shorts were not considered Logic and power/ground shorts were not considered Assumed that all defects are randomly distributed Assumed that all defects are randomly distributed Assumed that all defects can be corrected with a single row/column Assumed that all defects can be corrected with a single row/column Switch area was not accounted for our yield model Switch area was not accounted for our yield model Area results for CGR are approximated Area results for CGR are approximated

33Field-Programmable Technology (FPT) '05 Conclusions CGR effective for 1 or 2 defects CGR is effective for 1 or 2 defects FGR meets desired objectives: FGR meets desired objectives: Tolerates multiple randomly distributed defects Tolerates multiple randomly distributed defects Defect correction does not perturb timing Defect correction does not perturb timing Tolerates an increasing number of defects as array size increases Tolerates an increasing number of defects as array size increases Correction can be applied quickly Correction can be applied quickly

Thank you!

35Field-Programmable Technology (FPT) '05 Summary As the density of FPGAs increase, they becoming in susceptible to manufacturing defects As the density of FPGAs increase, they becoming in susceptible to manufacturing defects Fault-redundant techniques alleviate this growing problem Fault-redundant techniques alleviate this growing problem Depending on the desired level of protection, we can apply different techniques Depending on the desired level of protection, we can apply different techniques At low defect rates, the spare row and column approach has lower overhead than the fine-grain approach At low defect rates, the spare row and column approach has lower overhead than the fine-grain approach At large array sizes, the spare row and column approach requires more area overhead to tolerate the same number of defects as the fine-grain approach At large array sizes, the spare row and column approach requires more area overhead to tolerate the same number of defects as the fine-grain approach