RISC

Rational Behind RISC Few of the complex instructions were used –data movement – 45% –ALU ops – 25% –branching – 30% Cheaper memory VLSI technology (Very Large Scale Integration Fewer transistors on chip (lower cost) –use the space for pipelines, cache, registers

RISC VS CISC RISC –multiple register sets –3 operands –efficient parameter passing –single cycle instructions –hardwired control –fixed length instructions –highly pipelined –few, simple instructions –complexity in compiler –only load and store access memory –few addressing modes CISC –single register set –2 operands –inefficient parameter passing –multiple-cycle instructions –microprogrammed control –variable length instructions –less pipelined –many complex instructions –complexity in microcode –many instructions can access memory –many addressing modes

RISC vs. CISC continued RISC –emphasis on software –register to register load and store –large code size –low cycles/second –more transistors used on memory registers CISC –emphasis on hardware –memory to memory load and store –small code size –high cycles/second –transistors used for complex instructions

Assembly Language RISC multiply Load A, memory Load B, memory Prod A, B Store memory, A CISC multiply MULT memory, memory

Pipelining standard feature in RISC processors like an assembly line instruction execution is faster

Laundry Analogy

Laundry Analogy 2

RISC Pipelines Five Steps –fetch instruction from memory –read registers and decode instructions –execute the instruction or calculate an address –access an operand in data memory –write the result to a register

Pipeline Problems Data dependency –an instruction depends on the result of a previous instruction –example add $r3, $r2, $r1 add $r5, $r4, $r3 Solution –code reordering –no-op insertion –stall insertion

Problems continued Branch instructions –determine next instruction based on results of another instruction –example Loop : add $r3, $r2, $r1 sub $r6, $r5, $r4 beq $r3, $r6, Loop Solution –branch prediction

Pipeline Advancements Superpipelining Superscalar pipelining VLIW Dynamic pipeline scheduling Dynamic pipelines

Today’s Chips Increasingly difficult to categorize Post-RISC era increased processor speeds VLSI Examples –Intel IA-64 architecture –PowerPC

Recent Developments Simultaneous Multithreading –multiple threads execute at the same time –instructions from different threads are pulled into the pipeline –no one thread dominates the processor Value Prediction –prediction of value a load will produce