Network-on-Chip Links and Implementation Issues System-on-Chip Group, CSE-IMM, DTU.

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Presentation transcript:

Network-on-Chip Links and Implementation Issues System-on-Chip Group, CSE-IMM, DTU

© System-on-Chip Group, CSE-IMM, DTU 2 DSM and Clocking Issues Leakage current Parasitic capacitance Wire delay for global communication Cross talk/Inter-symbol interference Soft errors Meta-stability Global synchrony

© System-on-Chip Group, CSE-IMM, DTU 3 Overview Router Implementations Link Wire segmentation Encoding Virtual Channels Implementation

© System-on-Chip Group, CSE-IMM, DTU 4 Router Implementation Currently most methods focus on synchronous routers/switches for NoC Support programmability LUT are popular Slot-based reservation for service guarantees Current handling of multiple incoming channels is a challenge

© System-on-Chip Group, CSE-IMM, DTU 5 Thin vs Square Switch

© System-on-Chip Group, CSE-IMM, DTU 6 Network Link Provides raw bandwidth Datagram Flit (logical datum) or Phif (physical datum transferred in one step) Need mechanism to avoid deadlock and congestion since many inputs may be multiplex on a single link (shared)

© System-on-Chip Group, CSE-IMM, DTU 7 Virtual Channels Popular in macro-computer networks Improves better link utilization Basic functions is for deadlock avoidance A very useful tool for QoS realization Logically division of link bandwidth Priority arbitration of link access

© System-on-Chip Group, CSE-IMM, DTU 8 Virtual Channel Implementation Slot loading in synchronous environment Y X Z X2

© System-on-Chip Group, CSE-IMM, DTU 9 Link Segmentation

© System-on-Chip Group, CSE-IMM, DTU 10 Encoding Reduces power usage per communicated bit, while maintaining high speed and good noise margin M-of-N encodings, utilized fewer power at the cost of extra wires

© System-on-Chip Group, CSE-IMM, DTU 11 Overcoming DSM Issues Encoding Possible Shielding Differential signaling Link-level error correction (parity check)

© System-on-Chip Group, CSE-IMM, DTU 12 Network Implementation Synchronous vs Asynchronous Sync: Very high speeds possible, due to small critical path within routing nodes Tool support Difficult to achieve global synchrony Leakage power Examples: Æthereal, xpipes, SPIN, etc

© System-on-Chip Group, CSE-IMM, DTU 13 Network Implementation (cont.) Asynchronous: No idle power Encoding friendly Marginally larger circuit size Leakage power Examples: CHAIN

© System-on-Chip Group, CSE-IMM, DTU 14 Conclusion Many NoC implementation are synchronous, though it will face limitations of clock distribution Network is roughly 2-6.6% of total chip area Links realized via virtual channels has many advantages Asynchronous implementation are favorable Managing physical DSM issue critical for successful NoC implementation

© System-on-Chip Group, CSE-IMM, DTU 15 References BJERREGAARD, T. and MAHADEVAN, S “NoC Survey Manuscript”, Submitted. BAINBRIDGE, J. and FURBER, S Chain: A delay-insensitive chip area interconnect. IEEE Micro. BAINBRIDGE, W. and FURBER, S Delay insensitive system-on-chip interconnect using 1-of-4 dataencoding. In Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems (ASYNC’01). VAIDYA, R. S., SIVASUBRAMANIAM, A., and DAS, C. R Impact of virtual channels and adaptive routing on application performance. IEEE Transactions on Parallel and Distributed Systems. ZHANG, H., GEORGE, V., and RABAEY, J. M Low-swing on-chip signaling techniques: Effectiveness and robustness. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. MIZUNO, M., DALLY, W. J., and ONISHI, H Elastic interconnects: Repeater-inserted long wiring capable of compressing and decompressing data. In International Solid-State Circuits Conference. MUTTERSBACH, J., VILLIGER, T., and FICHTNER, W Practical design of globally- asynchronous locally-synchronous systems. In Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000 (ASYNC 2000). IEEE Computer society. COLE, R. J., MAGGS, B. M., and SITARAMAN, R. K On the benefit of supporting virtual channels in wormhole routers. Journal of Computer and System Sciences.