1. Network-on-Chip A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling System-on-Chip Group, CSE-IMM, DTU

2. © System-on-Chip Group, CSE-IMM, DTU 2 Modeling Asynchronous Circuits Balsa Tangram CHP Verilog VHDL SystemC Asynchronous CommunityIndustry Standard

3. © System-on-Chip Group, CSE-IMM, DTU 3 Paper Contribution Modeling and simulation of asynchronous circuits at different and mixed level of abstraction using SystemC Provide a Channel model that supports different data-types and protocols for seamless design flow

4. © System-on-Chip Group, CSE-IMM, DTU 4 Overview Motivation  Modeling Asychronous Circuits at Different Levels of Abstraction Channel Model Requirements  Channel Phases to Capture Communication Order  Translation to Physical Asynchronous Protocol Channel Model Implementation Illustration of Channel Usage in Asynchronous Network-on-Chip Design Conclusions

5. © System-on-Chip Group, CSE-IMM, DTU 5 Design Iteration Producer Send(data) Consumer Receive(data) High-level Model Consumer Handshake Control Data Storage Producer Handshake Control Data Storage Low-level Model Consumer Handshake Control Data Storage Producer Send(data) Mixed-level Model Consumer Producer Mixed-level Model Handshake Control Data Storage Receive(data) Channel

6. © System-on-Chip Group, CSE-IMM, DTU 6 Design Iteration Producer Send(data) Consumer Receive(data) High-level Model Consumer Handshake Control Data Storage Producer Handshake Control Data Storage Low-level Model Consumer Handshake Control Data Storage Producer Send(data) Mixed-level Model Consumer Producer Mixed-level Model Handshake Control Data Storage Receive(data) Channel

7. © System-on-Chip Group, CSE-IMM, DTU 7 Channel Behaviour SETUPRECOVERTRANSFERSETUPRECOVER TRANSFER Channel Phase IDLE Channel Data VALID XXX send(); receive(); send(); receive(); Module Calls VALIDXXX req ack Data VALID Abstract Channel Behaviour Used in High-Level Model Physical Channel Behaviour (4-ph-bd) Used in Low-Level Model

8. © System-on-Chip Group, CSE-IMM, DTU 8 Producer Channel Design ch_phase Data Lines Translator Protocol-Independent Channel 4-phase-bundled-data Channel ack req data send() probe() send_if recieve() probe() receive_if Abstract Interface Consumer Real Interface Abstract to physical data flow

9. © System-on-Chip Group, CSE-IMM, DTU 9 Channel Design ch_phase Data Lines Translator Protocol-Independent Channel 4-phase-bundled-data Channel ack req data send() probe() send_if recieve() probe() receive_if Producer Real Interface Consumer Abstract Interface Physical to abstract data flow

10. © System-on-Chip Group, CSE-IMM, DTU 10 Channel Design ch_phase Data Lines Translator Protocol-Independent Channel 4-phase-bundled-data Channel ack req data send() probe() send_if recieve() probe() receive_if Producer Real Interface Consumer Real Interface Physical to physical data flow

11. © System-on-Chip Group, CSE-IMM, DTU 11 Abstract to Physical Channel Translation send(); SETUP TRANSFERRECOVERIDLE req ack phase Procedural Call data VALIDXXX Consumer Handshake Control Data Storage Producer Send(data)

12. © System-on-Chip Group, CSE-IMM, DTU 12 Channel Usage in NoC Store-and-forward, TorusWormhole, Grid X-bar Abstract Physical Mixed- Mode Channel Library

13. © System-on-Chip Group, CSE-IMM, DTU 13 Conclusions Channel concept: that allows abstract, mixed and physical communication which enables the modeling and simulation of asynchronous protocols Channel implementation: supports seamless design refinement realized in SystemC Channel Usage: Applied in top-down design methodology for asynchronous networks-on-chip design

14. © System-on-Chip Group, CSE-IMM, DTU 14 References 1. J. Sparsø, S. Furber, “Principles of Asynchronous Circuit Design,” Chapter 8, Kluwer Academic Pub. 2001 2. M. Pedersen, “Asynchronous Design Using Plain VHDL in a Standard CAD-tool Framework”, ACiD-WG Workshop, 1999 3. A. Saifhashemi, “Verilog HDL: A Replacement for CSP”, ACiD-WG, 2003 4. A. Bardsley and D. Edwards, “Compiling the language Balsa to delay-insensitive hardware”, Hardware Description Languages and their Applications, 1997 5. K. v Berkel, J. Kessels, M. Roncken, R. Saeijs, and F. Schalij, “The VLSI- Programming Language Tangram and Its Translation into Handshake Circuits”, 1991 6. W. J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks”, DAC, 2001 7. SystemC Workgroup, http://www.systemc.org 8. T. Grötker, S. Liao, G. Martin, and S. Swan, “System Design with SystemC,” Kluwer Academic Pub., 2002 9. T. Fitzpatrick, “SystemVerilog for VHDL Users”, DATE, 2004