1. Network-on-Chip System-level Issues System-on-Chip Group, CSE-IMM, DTU

2. © System-on-Chip Group, CSE-IMM, DTU 2 System-View of SoC Master Slave Master Slave Master

3. © System-on-Chip Group, CSE-IMM, DTU 3 Overview Architectural Issues Communication Modeling Modeling Techniques Abstractions Traffic Charactersization

4. © System-on-Chip Group, CSE-IMM, DTU 4 Architectural Issues Impact on NoC: Message size Network geometry Implementation (GALS)

5. © System-on-Chip Group, CSE-IMM, DTU 5 Communication Description Message Passing Data structures communicated via unique channels Shared Memory Abstraction Read and Write to memory locations

6. © System-on-Chip Group, CSE-IMM, DTU 6 System-level NoC Modeling Techniques Techniques Analytical or Simulation models Abstractions Message passing or Shared memory Tools RTOS, communication task-graph, network processors, bit/cycle-true

7. © System-on-Chip Group, CSE-IMM, DTU 7 Communication Abstrations/Semantics LayerInterface semanticsImplementationCommunication Application/ Presentation IP-to-IP massaging sys.send(stuct myData) sys.receive(stuct myData) ApplicationMessage passing Session/ Transport IP-to-IP port-oriented messaging nwk.read(messagepointer*, unsigned len) nwk.write(int addr, msgptr*, unsigned len) OS kernel or Driver Message passing or shared memory NetworkNA-to-NA packet streams ctrl.send(), ctrl.receive() link.read(bit[] path, bit[] data_packet) link.write(bit[] path, bit[] data_packet) OS kernel or Driver/HAL Message passing or shared memory LinkNode-to-Node logical links ctrl.send(), ctrl.receive() channel.transmit(bit[] link, bit[] data_flit) channel.receive(bit[] link, bit[] data_flit) HardwareMessage passing PhysicalPins and wires A.drive(0), D.sample(), clk.tick() HardwareSignaling

8. © System-on-Chip Group, CSE-IMM, DTU 8 “Traffic Density” lowhigh Time Consumed during theComm. Event (time units) typical low IO Cores Memory Computation Intensive Cores DSP Type Cores Traffic Distribution

9. © System-on-Chip Group, CSE-IMM, DTU 9 Traffic Characterization Latency-critical: Latency-critical traffic is traffic with stringent latency demands such as for critical interrupts, memory access, etc. These often have low payload, Data-streams: Data streaming traffic have high payload and demand QoS in terms of bandwidth. Most often it is large, mostly fixed bandwidth which may be jitter critical. Examples are MPEG data, DMA access, etc. Best-effort: The best-effort traffic, is traffic with no specific requirements of commitment from the network.

10. © System-on-Chip Group, CSE-IMM, DTU 10 Common NoC Examples

11. © System-on-Chip Group, CSE-IMM, DTU 11 NoC Performance Evaluation A single of the performance parameters is not sufficient to describe NoC behavior Common terms:latency, bandwidth, jitter, power consumption and area usage For complete system analysis, benchmark are useful and many from macro-computer network have proven useful Beside performance evaluation, correct presentation of results of a multi-facet NoC is crucial

12. © System-on-Chip Group, CSE-IMM, DTU 12 Conclusion System-level modeling is useful for early evaluation of trade-offs such as mesh vs torus topology, etc Message passing is commonly implemented for NoCs at higher abstractions where as shared memory view is common for programers For NoC evaluation, only realistic traffic pattern is required from system-level modeling One or more of the latency-critical, streaming or best-effort is predominate in the network Simulation speed, accuracy and abstractions are key issues in NoC modeling NoC should be application specific implementation

13. © System-on-Chip Group, CSE-IMM, DTU 13 References T. Bjerregaard and S. Mahadevan, “NoC Survey Manuscript”, Submitted MAI, K., PAASKE, T., JAYASENA, N., HO, R., DALLY, W. J., and HOROWITZ, M. 2000. Smart memories: A modular reconfigurable architecture. In Proceedings of 27th International Symposium on Computer Architecture. BOLOTIN, E., CIDON, I., GINOSAR, R., and KOLODNY, A. 2004. Qnoc: Qos architecture and design process for network on chip. Jornal of System Architectures. CATTHOOR, F., CUOMO, A., MARTIN, G., GROENEVELD, P., RUDY, L., MAEX, K., DE STEEG, P. V., and WILSON, R. 2004. How can system level design solve the interconnect technology scaling problem. In Proceedings of DATE2004, IEEE Conference on Design, Automation and Test in Europe. MADSEN, J., MAHADEVAN, S., VIRK, K., and GONZALEZ, M. 2003. Network-on-chip modeling for systemlevel multiprocessor simulation. In Proceedings of the 24th IEEE International Real-Time Systems Symposium(RTSSŠ03). GERSTLAUER, A. 2003. Communication abstractions for system-level design and synthesis. Tech. rep., Center for Embedded Computer Systems, University of California, Irvine, CA 92697-3425, USA. JUURLINK, B. H. H. and WIJSHOFF, H. A. G. 1998. A quantitative comparison of parrallel computation models. ACM Transactions on Computer Systems. KARIM, F., NGUYEN, A., DEY, S., and RAO, R. 2001. On-chip communication architecture for oc-768 network processors. In Proceedings of 38th Design Automation Conference (DAC’01). LAHIRI, K., RAGHUNATHAN, A., and DEY, S. 2001. Evaluation of the traffic-performance characteristics of system- on-chip communication architectures. In Proceedings of the 14th International Conference on VLSI Design. LOGHI, M., ANGIOLINI, F., BERTOZZI, D., BENINI, L., and ZAFALON, R. 2004. Analyzing on-chip communication in a mpsoc environment. In Proceedings of the 2004 Design, Automation and Test in Europe Conference (DATE’04). IEEE. WIEFERINK, A., KOGEL, T., LEUPERS, R., ASCHEID, G., MEYR, H., BRAUN, G., and NOHL, A. 2004. A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition Volume II (DATE’04). IEEE Computer Society.