CS 630: Advanced Microcomputer Programming Spring 2004 Professor Allan B. Cruse University of San Francisco.

Slides:



Advertisements
Similar presentations
Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness.
Advertisements

Using VMX within Linux We explore the feasibility of executing ROM-BIOS code within the Linux x86_64 kernel.
Computer Organization and Assembly Languages Yung-Yu Chuang
Khaled A. Al-Utaibi  Computers are Every Where  What is Computer Engineering?  Design Levels  Computer Engineering Fields  What.
Crafting a ‘boot time’ program How we can utilize some standard ‘real-mode’ routines that reside in the PC’s ROM-BIOS firmware.
COS318 Lec 21 Operating System Structures Vivek Pai Princeton University.
Lecture 6 Machine Code: How the CPU is programmed.
CS 630: Advanced Microcomputer Programming Fall 2006 Professor Allan B. Cruse University of San Francisco.
Operating Systems: Segments 1 Segmentation Hardware Support single user program system: – wish somehow to relocate address 0 to after operating system.
1 Operating Systems and Protection CS Goals of Today’s Lecture How multiple programs can run at once  Processes  Context switching  Process.
IA-32 Processor Architecture
11/13/01CS-550 Presentation - Overview of Microsoft disk operating system. 1 An Overview of Microsoft Disk Operating System.
Defining protected-mode segment-descriptors An example of a protected-mode bootsector application that draws a message to the video display.
COS318 Lec 21 Operating System Structures Vivek Pai Princeton University.
Venturing into protected-mode A first look at the CPU registers and instructions which provide the essential supporting infrastructure.
CS 630: Advanced Microcomputer Programming Fall 2008 Professor Allan B. Cruse University of San Francisco.
1 Hardware and Software Architecture Chapter 2 n The Intel Processor Architecture n History of PC Memory Usage (Real Mode)
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture.
“Virtual” Memory How does the OS kernel provide “private” and “shared” memory areas to multiple concurrent processes?
PC hardware and x86 3/3/08 Frans Kaashoek MIT
1 ICS 51 Introductory Computer Organization Fall 2006 updated: Oct. 2, 2006.
CS2422 Assembly Language & System Programming November 2, 2006.
Assembly Language for Intel-Based Computers Chapter 2: IA-32 Processor Architecture Kip Irvine.
Understanding POST and ROM-BIOS service functions Numerous low-level services are available to real-mode programs (include boot-loaders)
Chapter 2: Impact of Machine Architectures What is the Relationship Between Programs, Programming Languages, and Computers.
CS2422 Assembly Language & System Programming September 22, 2005.
What is Assembly Language? Introduction to the GNU/Linux assembler and linker for Intel Pentium processors.
ICS312 Set 3 Pentium Registers. Intel 8086 Family of Microprocessors All of the Intel chips from the 8086 to the latest pentium, have similar architectures.
Microprocessor Systems Design I Instructor: Dr. Michael Geiger Spring 2012 Lecture 2: 80386DX Internal Architecture & Data Organization.
© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture.
Administrative Overview 6 Projects Design Review: Monday before 6:30pm Lab Friend Center 010 (“Fishbowl”)
Assembly Language for x86 Processors 6 th Edition Chapter 2: x86 Processor Architecture (c) Pearson Education, All rights reserved. You may modify.
An Introduction to IA-32 Processor Architecture Eddie Lopez CSCI 6303 Oct 6, 2008.
Assembly Language for Intel-Based Computers, 5th Edition
System Calls 1.
Assembly Language for Intel-Based Computers, 4 th Edition Chapter 2: IA-32 Processor Architecture (c) Pearson Education, All rights reserved. You.
6.828: PC hardware and x86 Frans Kaashoek
The Pentium Processor.
The Pentium Processor Chapter 3 S. Dandamudi To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Second Edition, Springer,
The Pentium Processor Chapter 3 S. Dandamudi.
Laface Operating System Design Booting a PC to run a kernel from Low memory VGA display.
Fall 2012 Chapter 2: x86 Processor Architecture. Irvine, Kip R. Assembly Language for x86 Processors 6/e, Chapter Overview General Concepts IA-32.
INSTRUCTION SET AND ASSEMBLY LANGUAGE PROGRAMMING
Chapter 2 Instruction Addressing and Execution. Lesson plan Review some concepts in the first week First assembly program with EMU8086 Related concepts.
CET 3510 Microcomputer Systems Tech. Lecture 2 Professor: Dr. José M. Reyes Álamo.
Chapter 2 Parts of a Computer System. 2.1 PC Hardware: Memory.
4. Kernel and VGA ENGI 3655 Lab Sessions. Richard Khoury2 Textbook Readings  None.
Sahar Mosleh California State University San MarcosPage 1 Intel IA-32 Architecture This lecture describes the architecture of the Intel IA-32 processor.
X86 Assembly Language We will be using the nasm assembler (other assemblers: MASM, as, gas)
Introduction to Intel IA-32 and IA-64 Instruction Set Architectures.
1 x86 Programming Model Microprocessor Computer Architectures Lab Components of any Computer System Control – logic that controls fetching/execution of.
Lecture 2. General-Purpose Computer Systems Prof. Taeweon Suh Computer Science Education Korea University ECM586 Special Topics in Embedded Systems.
Computer Organization & Assembly Language University of Sargodha, Lahore Campus Prepared by Ali Saeed.
BITS Pilani Pilani Campus Pawan Sharma Lecture / ES C263 INSTR/CS/EEE F241 Microprocessor Programming and Interfacing.
The Microprocessor & Its Architecture A Course in Microprocessor Electrical Engineering Department Universitas 17 Agustus 1945 Jakarta.
Chapter 2 Instruction Addressing and Execution. Lesson plan Review some concepts in the first week First assembly program with EMU8086 Related concepts.
Chapter Overview General Concepts IA-32 Processor Architecture
Assembly language.
x86 Processor Architecture
Computer Organization & Assembly Language Chapter 3
Basic Microprocessor Architecture
Homework Reading Continue work on mp1
Introduction to Assembly Language
BIC 10503: COMPUTER ARCHITECTURE
Introduction to Intel IA-32 and IA-64 Instruction Set Architectures
CS 301 Fall 2002 Computer Organization
The Microprocessor & Its Architecture
Assembly Language (CSW 353)
Computer Architecture CST 250
CSC 497/583 Advanced Topics in Computer Security
Presentation transcript:

CS 630: Advanced Microcomputer Programming Spring 2004 Professor Allan B. Cruse University of San Francisco

Course Synopsis We study the IA32 processor architecture It’s implemented in our Pentium 4 CPUs Also implemented in some earlier CPUs Not only Intel, but also AMD, Cyrix, clones Even present as ‘legacy mode’ in AMD64 For study purposes we can pretend we’re studying a ‘bare machine’ (i.e., no OS)

Point-of-View For study purposes we can pretend we’re studying a ‘bare machine’ (i.e., it just has standard PC hardware for doing I/O, and ROM-BIOS firmware supplied by vendor, but lacks any operating system software. So we get to ‘build our own’ miniature OS Doing this will bring us face-to-face with the CPU’s most fundamental capabilities

Methodology Our interactive computer classroom lets us take a ‘hands on’ approach to our studies (i.e., we combine ‘theory’ with ‘practice’) Typically we’ll devote first part each class to a ‘lecture’ about aspects of IA32 theory Then we’ll take time in the second part of class for ‘laboratory exercises’ that put the newly learned ideas into program code

Prerequisites Experience with C / C++ programming Familiarity with use of Linux / UNIX OS Acquaintance with x86 assembly language –Knowledge of the x86 general registers –Awareness of the x86’s instruction-set Understand the CPU’s fetch-execute cycle Recall the ways memory is addressed

Review of System Diagram Central Processing Unit Main Memory I/O device I/O device I/O device I/O device system bus

Review of the x86 API EAX EBX ECX EDX ESI EDI EBP ESP General Registers (32-bits) CS DS ES FS GS SS Segment Registers (16-bits) EIP EFLAGS Program Control and Status Registers (32 bits)

Review of Instruction-Set Data-transfer instructions (mov, xchg, …) Control-transfer instructions (jmp, call, …) Arithmetic/Logic instructions (add, or, …) Shift/Rotate instructions (shr, rol, …) String-manipulation instructions (movs, …) Processor-control instructions (cli, hlt, …) Floating-point instructions (fldpi, fmul, …)

Review “Fetch-Execute” Cycle ESP EIP Program Instructions (TEXT ) Program Variables (DATA ) Temporary Storage (STACK) main memory central processor EAX the system bus

Review of memory addressing Implicit addressing (e.g. push eax, scasb, xlat, …) Direct addressing (e.g., inc salary, mov counter,#0, …) Indirect addressing (e.g., add [ebx],cl, pop word [bx+si]

Course Textbook Tom Shanley, Protected Mode Software Architecture, Addison-Wesley (1996) Initial reading assignment: Week 1: Read Part One (Chapters 1-3) Week 2: Read Part Two (Chapters 4-5)

Instructor Contact Information Office: Harney Science Center – 212 Hours: Mon-Wed 2:30pm-4:00pm Phone: (415) Webpage: nexus.cs.usfca.edu/~cruse

CPU Execution Modes REAL MODE PROTECTED MODE VIRTUAL 8086 MODE SYSTEM MANAGEMENT MODE POWER-ON / RESET

Early Intel Processors 1971: 4004 (first 4-bit processor) 1972: 8008 (first 8-bit processor) 1974: 8080 (widely used by CP/M) 1978: 8086/8088 (first 16-bit processor) 1982: 80286: (introduced protected mode) 1985: 80386: (first 32-bit processor) 1989: 80486: (integrated floating-point)

Recent Intel Processors 1993: Pentium processor (dual CPUs) 1995: Pentium Pro (for high-end servers) 1996: Pentium II (single-edge connector) 1998: Pentium II Xeon (multiple CPUs) 1999: Celeron (stripped down Pentium II) 1999: Pentium III (1GHz, 512K L2 cache) 1999: Pentium III Xeon (high-end servers) 2000: Pentium 4 (new SIMD instructions)

Backward Compatibility From its first commercial success onward, “backward compatibility” (i.e., support for the software legacy) has been viewed by Intel as an engineering design imperative So the first 16-bit processors (8086/8088), used in IBM-PCs, were designed in a way that would let them run the vast number of CP/M programs written for 8-bit 8080 CPU

Real Mode 8086/8088 had only one execution mode It used “segmented” memory-addressing Physical memory on 8086 was subdivided into overlapping “segments” of fixed-size The length of any “segment” was 64KB, to match the size of an 8080s address-space This scheme supported CP/M applications (Our Pentium CPUs continue this support)

64KB Memory-Segments Fixed-size segments partially overlap Segments start on paragraph boundaries Segment-registers serve as “selectors” code data stack CS DS SS

Real-Mode Address-Translation 0x12340x6789 Logical address: 16-bit segment-address16-bit offset-address x x18AC9 20-bit bus-address Physical address: 0x x x18AC9

Protected Mode Any Pentium CPU starts up in ‘Real Mode’ While in real mode, its behavior is like an 8086 (i.e., any program can do anything it wants, as the CPU’s protection mechanisms are disabled) But software can enter ‘protected mode’ (on a or higher) using a special instruction to modify a bit within a processor control-register Once in protected mode, the segment-sizes can be adjusted, accesses to physical memory (or to peripheral devices) can be restricted, and tasks can be isolated from interfering with one another

Enabling Protection NENE ETET TSTS EMEM MPMP PEPE Machine Status Word PE (Protection Enable) 0=no, 1=yes SMSW AX OR AX, #1 LMSW AX Code-fragment that enables protection

Protected-Mode Segments Segments can have varying lengths Segments may or may not overlap Segments are assigned ‘access-attributes’ code data stack operating system CS DS SS GS

Our ‘bare machine’ If we want to do a “hands on” study of our CPU, without any operating system getting in our way, we have to begin by exploring ‘Real Mode’ (it’s the CPU’s startup state) We will need to devise a mechanism by which our programs can get loaded into memory (since we won’t have an OS) This means we must write a ‘boot loader’

What’s a ‘boot loader’ A ‘boot loader’ is a small program that is resident in the starting sector of a disk (or tape or other non-volatile storage medium) After testing and initializing the machine’s essential hardware devices, the startup program in the ROM-BIOS firmware will read the ‘boot loader’ into memory, at an assigned location, and then jump there

PC ROM-BIOS BOOT_LOCN BOOT_LOCN 0x00007C00 0x00007E bytes ROM-BIOS VRAM IVT and BDA 8086 memory-map RAM Vendor’s Firmware Video Display Memory No installed memory Volatile Program Memory 1-MB

Some Requirements A ‘boot loader’ has to be 512 bytes in size (because it has to fit within a disk sector) Must begin with executable machine-code Must end with a special ‘boot signature’ Depending on the type of storage medium, it may need to share its limited space with certain other data-structures (such as the ‘partition table’ on a hard disk, or the Bios Parameter Block’ on a MS-DOS diskette)

Writing a ‘boot loader’ Not practical to use a high-level language We need to use 8086 assembly language (our classroom system provides ‘as86’) This assembler’s syntax is similar to the standard set by Intel and Microsoft, but it differs from the AT&T-style syntax that is used with the Linux ‘as’ assembler Syntax is documented online: $ man as86

Using ROM-BIOS functions Our system firmware provides many basic service-functions that real mode programs can invoke (this includes boot-loaders): –Video display functions –Keyboard input functions –Disk access functions –System query functions –A machine ‘re-boot’ function

Example: Write_String function Setup parameters in designated registers –AH = function ID-number (e.g. 0x13) –AL = cursor handling method (e.g. 0x01) –BH = display page-number (e.g., 0x00) –BL = color attributes (e.g., 0x0A) –CX = length of the character-string –DH, DL = row-number, column-number –ES:BP = string’s starting-address (seg:off) Call BIOS via software interrupt (int-0x10)

Compiling and Installing Compiling our ‘boot loader’ using as86 is a one-step operation: $ as86 bootload.s –b bootload.b Installing our bootloader into the starting sector of a floppy diskette is also simple: $ dd if=bootload.b of=/dev/fd0

Executing a ‘boot-loader’ Perform a system reset (CTRL-ALT-DEL) Our classroom machines will load GRUB (the Linux GRand Unified Boot-loader) GRUB will display a menu of Boot Options You can choose to boot from floppy disk Another option: boot from a diskette-image

In-Class Exercises Go to our class website: Download, assemble, and install our demo ‘bootmsw.s’ Reboot machine and use GRUB’s menu to boot our demo from the floppy diskette Modify our demo so it will ‘reboot’ (instead of freeze) when a user presses any key

Programming Details It’s easy to include ‘await keypress’: mov ah,# 0; function-ID int0x16; BIOS keyboard service It’s easy to include ‘reboot system’: int0x19; BIOS reboot service

A valuable Online Reference Professor Ralf Brown’s Interrupt List (see webpage link under ‘Resources’) It tells how to make BIOS system-calls, to perform numerous low-level services from within Real-Mode 8086 applications (such as ‘boot loader’ programs)