An Efficient Test Data Reduction Technique Through Dynamic Pattern Mixing Across Multiple Fault Models 2011 VLSI Test Symposium S. Alampally 1, R. T. Venkatesh 2, P. Shanmugasundaram 2 R. A. Parekhji 1 and V. D. Agrawal 2 1 Texas Instruments, Bangalore (India) 2 Auburn University, Alabama (USA)

Outline Pattern optimization across fault models Concurrent ATPG flow Results Observations Conclusion 5/4/2011VLSI Test Symposium 20112

Testing costs overview Tester memory constraints Limited number of tester channels and channel bandwidth Cost of adding testability hardware on chip Reference: N. A. Touba, “Survey of Test Vector Compression Techniques,” IEEE Design & Test of Computers, Vol. 23, pp , Apr /4/2011VLSI Test Symposium 20113

Pattern optimization across fault models Stuck-At Transition Path Delay Bridging Methodology Optimized Pattern Set 5/4/2011VLSI Test Symposium 20114

Prior work on pattern reuse 1.N. Yogi and V. Agrawal [1] explored the use of hybrid LP-ILP for static pattern optimization. -Experiments were carried out on ISCAS89 benchmarks. -Stuck-at, transition and IDDQ combinations were considered. -More than 50% reduction in pattern count was achieved. 2.S. Goel and R. Parekhji [2] described a technique for pattern optimization for delay faults. -Path delay, transition fault and stuck-at models were considered. -Benefit of (ΔA + ΔB + C) versus (A + B + C). -Pattern count reductions of up to 37% were observed. -Employed by several teams in TI. 3.We will later compare the advantage of the current work against [2]. [1] N. Yogi and V. D. Agrawal, “N-Model Tests for VLSI Circuits,” Proc. 40 th IEEE Southeastern Symposium on System Theory, pp , March [2] S. Goel and R. A. Parekhji, “Choosing the Right Mix of At-Speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency,” Proc. 14 th IEEE Asian Test Symposium, pp , Dec /4/2011VLSI Test Symposium 20115

Concurrent ATPG flow with example Pattern Limit 32 Stuck-at modelTransition model Step 1FC S = 0, Fault Set F S FC T = 0, Fault Set F T Step 2IFC S = 58, Pattern Set P S IFC T = 48, Pattern Set P T Step 3IFSC(P T, F S ) = 50IFSC(P S, F T ) = 45 Step 4SP S = 30SP T = Conclusion: Stuck-At pattern set is more effective in this interval and is chosen against the Transition pattern set. Pattern Limit 32 Stuck-At modelTransition model Step 1FC S = 0+58 = 58, F S FC T = 0+45 = 45, F T Step 2IFC S = 25, P S IFC T = 20, P T Step 3IFSC(P T, F S ) = 22IFSC(P S, F T ) = 15 Step 4SP S = 24SP T = Conclusion: Transition pattern set is more effective in this interval and is chosen against the Stuck-at pattern set. Pattern interval 1 Pattern interval 2 Pattern Limit 32 Stuck-At modelTransition model Step 1FC S = = 80, F S FC T = = 65, F T Pattern interval 3 5/4/2011VLSI Test Symposium 20116

Saved patterns metric Pattern set that is chosen and saved in an interval is decided based on an effectiveness criteria. SP S (Saved Patterns) is defined as the number of patterns saved if pattern set P S is chosen over the other set P T. This effectiveness criteria is computed as, SP S = IFSC(P S,F T ) * P T /IFC T and SP T = IFSC(P T,F S ) * P S /IFC S. The pattern set that gives the ‘highest’ savings in an interval is chosen and saved based on this metric. 5/4/2011VLSI Test Symposium 20117

Designs used for evaluating the concurrent ATPG flow Design Flip-flop count Gate count (in millions) ATPG technique A219,5744.0LOC B240,0002.5LOS C33,7920.4LOS Concurrent ATPG runs were conducted using different fault model combinations and the results were analyzed. 5/4/2011VLSI Test Symposium 20118

Results in non-compression mode Design Fault model combinations Test coverage % Pattern Count% Reduction w.r.t Un- optimized Optimized using [2] Concurr- ent ATPG Un- optimized [2] A Transition Dynamic Bridging Path delay Final Pattern Count A Transition Dynamic Bridging Final Pattern Count A Small Delay Dynamic Bridging Path delay Final Pattern Count C Stuck-at Transition Final Pattern Count /4/2011VLSI Test Symposium 20119

Results with test compression Design Fault model combinations Test cov. (%) Pattern Count (DFTMAX) / Intervals (DBIST) % Reduction w.r.t. Un- optimized Optimized using [2] Concurr- ent ATPG Un- optimized [2] A Transition Dynamic Bridging Final Pattern Count B Stuck-At Transition Static Bridging Dynamic Bridging Final Pattern Count C Stuck-At Transition Final Pattern Count /4/2011VLSI Test Symposium

Observations Transition fault coverage when run along with dynamic bridging and path delay fault models. Bridging fault coverage when run along with transition and path delay fault models. When compared against just summing up patterns across fault models and also the technique of [2], concurrent ATPG provides good benefit for designs irrespective of the use of test compression. Percentage reduction in pattern count was lesser with designs using test compression when compared to the same designs without enabling compression. 5/4/2011VLSI Test Symposium

Observations When path delay model is used with two other models with the concurrent ATPG, it gets sidelined due to the domination by the other two. Run times can be large compared to the existing optimization technique because of the ATPG and fault-simulation runs at each interval. Path delay fault coverage when run along with transition and bridging fault models. 5/4/2011VLSI Test Symposium

Conclusion Test data volume and test time are critical components of test cost because of tester memory constraints. In this work an ATPG technique is proposed where all fault models are concurrently targeted in a single ATPG run and pattern count reduction is achieved. Reductions ranging from 21% to 68% were seen compared to the approach of just adding patterns across models (unoptimized). 3% to 36% improvements were seen over the existing optimization technique. 5/4/2011VLSI Test Symposium