Introduction to Logic Synthesis Alan Mishchenko UC Berkeley

2 Overview (1) Problems in logic synthesis (1) Problems in logic synthesis Representations and computations Representations and computations (2) And-Inverter Graphs (AIGs) (2) And-Inverter Graphs (AIGs) The foundation of innovative synthesis The foundation of innovative synthesis (3) AIG-based solutions (3) AIG-based solutions Synthesis, mapping, verification Synthesis, mapping, verification

3 (1) Problems In Synthesis What are the objects to be “synthesized”? What are the objects to be “synthesized”? Boolean functions (with or without don’t-cares) Boolean functions (with or without don’t-cares) State machines, relations, sets, etc State machines, relations, sets, etc How to represent them efficiently? How to represent them efficiently? Depends on the task to be solved Depends on the task to be solved Depends on the size of an object Depends on the size of an object How to create, transform, minimize the representations? How to create, transform, minimize the representations? Multi-level logic synthesis Multi-level logic synthesis Technology mapping Technology mapping Verification Verification

4 Terminology Logic function (e.g. F = ab+cd) Logic function (e.g. F = ab+cd) Variables (e.g. b) Variables (e.g. b) Minterms (e.g. abcd) Minterms (e.g. abcd) Cube (e.g. ab) Cube (e.g. ab) Logic network Logic network Primary inputs/outputs Primary inputs/outputs Logic nodes Logic nodes Fanins/fanouts Fanins/fanouts Transitive fanin/fanout cone Transitive fanin/fanout cone Cut and window (defined later) Cut and window (defined later) Primary inputs Primary outputs Fanins Fanouts TFO TFI

5 Logic (Boolean) Function Completely specified logic function Completely specified logic function Incompletely specified logic function Incompletely specified logic function  11111 On-setOff-setDC-set ab cd cd ab

6 Relations Relation (a1,a2)  (b1,b2) Relation (a1,a2)  (b1,b2) (0,0)  (0,0) (0,0)  (0,0) (0,1)  (1,0)(0,1) (0,1)  (1,0)(0,1) (1,0)  (1,1) (1,0)  (1,1) (1,1)  (1,0) (1,1)  (1,0) FSM FSM 0 01111 11 10100 a1 a2 b1 b Current state Next state Characteristic function

7 Representation Zoo Find each of these representations? Truth table (TT) Truth table (TT) Sum-of-products (SOP) Sum-of-products (SOP) Product-of-sums (POS) Product-of-sums (POS) Binary decision diagram (BDD) Binary decision diagram (BDD) And-inverter graph (AIG) And-inverter graph (AIG) Logic network (LN) Logic network (LN) abcdF F = ab+cd F = (a+c)(a+d)(b+c)(b+d) 10 a b c dF a bcdF a b c dFab x+cd

8 Representation Overview TT are the natural representation of logic functions TT are the natural representation of logic functions Not practical for large functions Not practical for large functions Still good for functions up to 16 variables Still good for functions up to 16 variables SOP is widely used in synthesis tools since 1980’s SOP is widely used in synthesis tools since 1980’s More compact than TT, but not canonical More compact than TT, but not canonical Can be efficiently minimized (SOP minimization by Espresso, ISOP computation) and translated into multi-level forms (algebraic factoring) Can be efficiently minimized (SOP minimization by Espresso, ISOP computation) and translated into multi-level forms (algebraic factoring) BDD is a useful representation discovered around 1986 BDD is a useful representation discovered around 1986 Canonical (for a given function, there is only one BDD) Canonical (for a given function, there is only one BDD) Very good, but only if (a) it can be constructed, (b) it is not too large Very good, but only if (a) it can be constructed, (b) it is not too large Unreliable (non-robust) for many industrial circuits Unreliable (non-robust) for many industrial circuits AIG is an up-and-coming representation! AIG is an up-and-coming representation! Compact, easy to construct, can be made “canonical” using a SAT solver Compact, easy to construct, can be made “canonical” using a SAT solver Unifies the synthesis/mapping/verification flow Unifies the synthesis/mapping/verification flow The main reason to give this talk The main reason to give this talk

9 Problem Size Time CNF TT SOPBDD Historical Perspective AIG Espresso, MIS, SIS SIS, VIS, MVSIS ABC

10 What Representation to Use? For small functions (up to 16 inputs) For small functions (up to 16 inputs) TT works the best (local transforms, decomposition, factoring, etc) TT works the best (local transforms, decomposition, factoring, etc) For medium-sized functions ( inputs) For medium-sized functions ( inputs) In some cases, BDDs are still used (reachability analysis) In some cases, BDDs are still used (reachability analysis) Typically, it is better to represent as AIGs Typically, it is better to represent as AIGs Translate AIG into CNF and use SAT solver for logic manipulation Translate AIG into CNF and use SAT solver for logic manipulation Interpolate or enumerate SAT assignments Interpolate or enumerate SAT assignments For large industrial circuits (>100 inputs, >10,000 gates) For large industrial circuits (>100 inputs, >10,000 gates) Traditional LN representation is not efficient Traditional LN representation is not efficient AIGs work remarkably well AIGs work remarkably well Lead to efficient synthesis Lead to efficient synthesis Are a natural representation for technology mapping Are a natural representation for technology mapping Easy to translate into CNF for SAT solving Easy to translate into CNF for SAT solving etc etc

11 What are Typical Transformations? Typical transformations of representations Typical transformations of representations For SOP, minimize cubes/literals For SOP, minimize cubes/literals For BDD, minimize nodes/width For BDD, minimize nodes/width For AIG, restructure, minimize nodes/levels For AIG, restructure, minimize nodes/levels For LN, restructure, minimize area/delay For LN, restructure, minimize area/delay

12 Computations in Networks / AIGs Divide-and-conquer Divide-and-conquer Traversal, windowing, cut computation Traversal, windowing, cut computation Guess-and-check Guess-and-check Bit-wise simulation Bit-wise simulation Reason-and-prove Reason-and-prove Boolean satisfiability Boolean satisfiability

13 Traversal Traversal is visiting nodes in the network in some order Traversal is visiting nodes in the network in some order Topological order visits nodes from PIs to POs Topological order visits nodes from PIs to POs Each node is visited after its fanins are visited Each node is visited after its fanins are visited Reverse topological order visits nodes from POs to PIs Reverse topological order visits nodes from POs to PIs Each node is visited after its fanouts are visited Each node is visited after its fanouts are visited Primary inputs Primary outputs Traversal in a topological order

14 Windowing Definition Definition A window for a node is the node’s context, in which an operation is performed A window for a node is the node’s context, in which an operation is performed A window includes A window includes k levels of the TFI k levels of the TFI m levels of the TFO m levels of the TFO all re-convergent paths between window PIs and window POs all re-convergent paths between window PIs and window POs Window POs Window PIs k = 3 m = 3 Pivot node

15 Structural Cuts in AIG A cut of a node n is a set of nodes in transitive fan-in such that every path from the node to PIs is blocked by nodes in the cut. A k-feasible cut means the size of the cut must be k or less. abc p q n The set {p, b, c} is a 3-feasible cut of node n. (It is also a 4-feasible cut.) k-feasible cuts are important in FPGA mapping because the logic between root n and the cut nodes {p, b, c} can be replaced by a k-LUT

16 Cut Computation a b c p q { {p}, {a, b} }{ {q}, {b, c} } { {a} } { {b} }{ {c} } n { {n}, {p, q}, {p, b, c}, {a, b, q}, {a, b, c} } The set of cuts of a node is a ‘cross product’ of the sets of cuts of its children. Any cut that is of size greater than k is discarded. Computation is done bottom-up (P. Pan et al, FPGA ’98; J. Cong et al, FPGA ’99) k Cuts per node

17 Bitwise Simulation Assign particular (or random) values at the primary inputs Assign particular (or random) values at the primary inputs Multiple simulation patterns are packed into 32- or 64-bit strings Multiple simulation patterns are packed into 32- or 64-bit strings Perform bitwise simulation at each node Perform bitwise simulation at each node Nodes are ordered in a topological order Nodes are ordered in a topological order Works well for AIG due to Works well for AIG due to The uniformity of AND-nodes The uniformity of AND-nodes Speed of bitwise simulation Speed of bitwise simulation Topological ordering of memory used for simulation information Topological ordering of memory used for simulation information a bcdF

18 Boolean Satisfiability Given a CNF formula  (x), satisfiability problem is to prove that  (x)  0, or to find a counter-example x’ such that  (x’)  1 Given a CNF formula  (x), satisfiability problem is to prove that  (x)  0, or to find a counter-example x’ such that  (x’)  1 Why this problem arises? Why this problem arises? If CNF were a canonical representation (like BDD), it would be trivial to answer this question. If CNF were a canonical representation (like BDD), it would be trivial to answer this question. But CNF is not canonical. Moreover, CNF can be very redundant, so that a large formula is, in fact, equivalent to 0. But CNF is not canonical. Moreover, CNF can be very redundant, so that a large formula is, in fact, equivalent to 0. Looking for a satisfying assignment can be similar to searching for a needle in the hay-stack. Looking for a satisfying assignment can be similar to searching for a needle in the hay-stack. The problem may be even harder, if there is no needle there! The problem may be even harder, if there is no needle there!

19 Example (Deriving CNF) (a + b + c) (a + b + c’) (a’ + b + c’) (a + c + d) (a’ + c + d) (a’ + c + d’) (b’ + c’ + d’) (b’ + c’ + d) ab cd Cube: bcd’ Clause: b’ + c’ + d CNF

20 SAT Solver The best SAT solver is MiniSAT ( The best SAT solver is MiniSAT ( Efficient (won many competitions) Efficient (won many competitions) Simple (600 lines of code) Simple (600 lines of code) Easy to modify and extend Easy to modify and extend Integrated into ABC Integrated into ABC SAT solver types SAT solver types CNF-based, circuit-based CNF-based, circuit-based Complete, incomplete Complete, incomplete DPLL, saturation, etc. DPLL, saturation, etc. A lot of magic is used to build an efficient SAT solver A lot of magic is used to build an efficient SAT solver Two literal clause watching Two literal clause watching Conflict analysis with clause recording Conflict analysis with clause recording Non-chronological backtracking Non-chronological backtracking Variable ordering heuristics Variable ordering heuristics Random restarts, etc Random restarts, etc Applications in EDA Applications in EDA Verification Verification Equivalence checking Equivalence checking Model checking Model checking Synthesis Synthesis Circuit restructuring Circuit restructuring Decomposition Decomposition False path analysis False path analysis Routing Routing

21 Example (SAT Solving) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) a (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) b c dd b c dd c d (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) (¬b + ¬c + ¬d) (a + b + c) (a + b + ¬c) (¬a + b + ¬c) (a + c + d) (¬a + c + d) (¬a + c + ¬d) (¬b + ¬c + d) Courtesy Karem Sakallah, University of Michigan

22 (2) And-Inverter Graphs (AIG) Definition and examples Definition and examples Several simple tricks that make AIGs work Several simple tricks that make AIGs work Sequential AIGs Sequential AIGs Unifying representation Unifying representation A typical synthesis application: AIG rewriting A typical synthesis application: AIG rewriting

23 AIG Definition and Examples cd ab F(a,b,c,d) = ab + d(ac’+bc) F(a,b,c,d) = ac’(b’d’)’ + c(a’d’)’ = ac’(b+d) + bc(a+d) cd a b nodes 4 levels 7 nodes 3 levels bcac a b d acbdbcad AIG is a Boolean network composed of two-input ANDs and inverters.

24 Three Simple Tricks Structural hashing Structural hashing Makes sure AIG is always stored in a compact form Makes sure AIG is always stored in a compact form Is applied during AIG construction Is applied during AIG construction Propagates constants Propagates constants Ensures each node is structurally unique Ensures each node is structurally unique Complemented edges Complemented edges Represents inverters as attributes on the edges Represents inverters as attributes on the edges Leads to fast, uniform manipulation Leads to fast, uniform manipulation Does not use memory for inverters Does not use memory for inverters Leads to efficient structural hashing Leads to efficient structural hashing Memory allocation Memory allocation Uses fixed amount of memory for each node Uses fixed amount of memory for each node Can be done by a simple custom memory manager Can be done by a simple custom memory manager Even dynamic fanout manipulation is supported! Even dynamic fanout manipulation is supported! Allocates memory for nodes in a topological order Allocates memory for nodes in a topological order Optimized for traversal in the same topological order Optimized for traversal in the same topological order Small static memory footprint for many applications Small static memory footprint for many applications ab c d ab c d Without hashing With hashing

25 Sequential AIGs Sequential networks have memory elements in addition to logic nodes Sequential networks have memory elements in addition to logic nodes Memory elements are modeled as D-flip-flops Memory elements are modeled as D-flip-flops Initial state {0,1,x} is assumed to be given Initial state {0,1,x} is assumed to be given Several ways of representing sequential AIGs Several ways of representing sequential AIGs Additional PIs and POs in the combinational AIG Additional PIs and POs in the combinational AIG Additional register nodes with sequential structural hashing Additional register nodes with sequential structural hashing Sequential synthesis (in particular, retiming) annotates registers with additional information Sequential synthesis (in particular, retiming) annotates registers with additional information Takes into account register type and its clock domain Takes into account register type and its clock domain

26 AIG: A Unifying Representation An underlying data structure for various computations An underlying data structure for various computations Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager Rewriting, resubstitution, simulation, SAT sweeping, induction, etc are based on the same AIG manager A unifying representation for the whole flow A unifying representation for the whole flow Synthesis, mapping, verification use the same data-structure Synthesis, mapping, verification use the same data-structure Allows multiple structures to be stored and used for mapping Allows multiple structures to be stored and used for mapping The main functional representation in ABC The main functional representation in ABC A foundation of new logic synthesis A foundation of new logic synthesis

27 AIG Rewriting a b a c Subgraph 1 b c a Subgraph 2 Pre-computing AIG subgraphs Consider function f = abc a c b Subgraph 3 Rewriting AIG subgraphs Rewriting node A Rewriting node B  a b a c  a b a c A Subgraph 1 b c a A Subgraph 2 b c a B a b a c B Subgraph 1 In both cases 1 node is saved AIG rewriting aims at minimizing the number of AIG nodes without increasing the number of AIG levels AIG rewriting aims at minimizing the number of AIG nodes without increasing the number of AIG levels

28 (3) AIG-Based Solutions Synthesis Synthesis Mapping Mapping Verification Verification

29 AIG-Based Solutions (Synthesis) Restructures AIG or logic network by the following transforms Restructures AIG or logic network by the following transforms Algebraic balancing Algebraic balancing Rewriting/refactoring/redecomposition Rewriting/refactoring/redecomposition Resubstitution Resubstitution Minimization with don't-cares, etc Minimization with don't-cares, etc Synthesis D2 D1 Synthesis with choices D3 HAIG D2 D1 D3D4 D4

30 AIG-Based Solutions (Mapping) Input: A Boolean network (And-Inverter Graph) Output: A netlist of K-LUTs implementing AIG and optimizing some cost function The subject graph The mapped netlist Technology Mapping a b cd f e a b cd e f

31 AIG-Based Solutions (Verification) Property checking Property checking Takes design and property and makes a miter (AIG) Takes design and property and makes a miter (AIG) Equivalence checking Equivalence checking Takes two designs and makes a miter (AIG) Takes two designs and makes a miter (AIG) The goal is to transform AIG until the output is proved constant 0 The goal is to transform AIG until the output is proved constant 0 D2 D1 Equivalence checking 0 D1 Property checking 0 p

32 Summary Introduced problems in logic synthesis Introduced problems in logic synthesis Representations and computations Representations and computations Described And-Inverter Graphs (AIGs) Described And-Inverter Graphs (AIGs) The foundation of innovative synthesis The foundation of innovative synthesis Overviewed AIG-based solutions Overviewed AIG-based solutions Synthesis, mapping, verification Synthesis, mapping, verification