Project name: Interface of DSP to Peripherals of PC Supervisor: Broodney, Hen | Presenting: Yair Tshop Michael Behar בס " ד

General Description בס " ד Project goal: Connecting The TI DSP to the computer Peripherals in order to connect the Peripherals to a computer through a Blue Tooth. Peripherals : 2 Ps/2 for mouse and KeyBoard Parallel port can use printers Rs232 com port USB for Low speed devices

Feasibility בס " ד In order to check the feasibility we consider the Pc Peripherals typical Bandwith: USB : Number 1 bandwidth consumer 12Mb/s or 1.5 Mb/s Rs232 : Operates typically in 9600b/s on PCs Parallel :10 KB/s Ps/2: several Kb/s Total Raw Bandwidth is 200KB/s

Bandwidth Discussion Blue Tooth Bandwidth ~300KB/s DSP McSBP is much faster :1.25 MB/s full duplex. Internal Altera bus 10 MB/s* For Parallel, additional bandwidth is needed, in order to pass control lines *for a 10 MHz clock בס " ד

Bottom line The Blue tooth Bandwidth (300 KB/s) permits us to work with the USB configured for 1.5Mb/s In this configuration we expect to be able to transfer all the peripheral through the system. בס " ד

Implementation Architecture בס " ד

Architecture Considerations The board has two functions : 1. On the computer side 2. On the peripherals side The internal bus size is 8 bit. The bus access is given by a Req and Grant policy. Data that is put on Int bus by the McBSP is tagged with 3 address bits. בס " ד

The Controller The controller is responsible for managing the arbitration of the internal bus. Each peripherals gets a part according to its bandwidth’s weight. A round robin insures that there will be no starvation. בס " ד

The McBSP block בס " ד

McBSP block tasks Full Duplex  Rx and Tx Models Multi channel operation (TDM) Each peripheral gets channels according to its bandwidth. Tx Model: Transfer Byte as serial bits Fit each Byte in its appropriate slot. Rx Model: Receive The bits and ensemble a Byte Produces a target address. בס " ד

Parallel block בס " ד

Parallel block tasks Two units :HCA & TCA Each unit contains an E ncoder & D ecoder. Encode each event into 8 bits code & vise versa. The control logic controls the: Fifos,Internal bus,Buffers בס " ד

Board

Status Block diagram Getting familiar with Parallel Port Protocol Getting familiar with McBSP Defining the internal bus arbitration and protocol Advanced Board schematics בס " ד

Future plan Final Board schematics Board production Parallel block implementation McBSP block implementation Parallel  McBSP  Parallel Simulation בס " ד

Part A final presentation A full working board A loop back of a parallel bus including the McBSP transmit and receive Two sources for the loop back in order to check the internal bus and slots in the McBSP