CS 140 Lecture 12 Professor CK Cheng 11/07/02

Part III - Standard Modules Decoder, Encoder, Mux, DeMux, Shifter, Adder, Multiplexer Interconnect: Decoder, Encoder, Mux, DeMux Operation: Addition, Multiplication, Shift P1 Memory Mux, 8 mem module in the bank P2 Pk Demux Decoder Mux Data Address

1. Decoder 0 y0y1y7y0y1y7 I0I0 I1I1 I2I EN (enable) n inputs 2 n outputs If En = 1 y i = 0 if (I 2, I 1, I 0 ) = i y i = 1 if (I 2, I 1, I 0 ) = i Else y i = 0 for all i. n - 2 n decoder....

Logic Diagram y0y0 I2’I2’ I1’I1’ I0’I0’ y1y1 I2I2 I1’I1’ I0’I0’ En y7y7 I2I2 I1I1 I0I0.... y 0 = 1 if (I 2, I 1, I 0 ) = (0,0,0) & EN = 1 y i = I 0 ’I 1 ’I 2 ’EN

Application: Decoder and OR as a universal set. Implement: f 1 (a,b,c) =  m (1,2,4) f 2 (a,b,c) =  m (2,3) f 3 (a,b,c) =  m (0,5,6) with a 3 –input decoder and OR gates. I0I0 y0y1..y7y0y1..y7 c b a I1I1 I2I Eny1y1 y2y2 y3y3 f1f1 y2y2 y3y3 f2f2 y0y0 y7y7 f3f3 y5y5

Tree of decoders Implement a decoder with decoders. I0I0 y0y1y7y0y1y7 I1I1 I2I I0I0 y 8 y 9 y 15 I1I1 I2I d a b c

Implement a decoder with decoders. En D0D0 I 2, I 1, I 0 D1D1 y0y0 y7y7 y8y8 y 15 D7D7 y 56 y 63 En I 2, I 1, I 0 I 5, I 4, I 3

1. Encoder y n-1 En A I 2 n -1 8 inputs 3 outputs y0y0 y1y1 y2y En At most one I i = 1. (y n-1,.., y 0 ) = i if I i = 1 &  n = 1 0 otherwise. A = 1 if En = 1 and i s.t. I i = 1 0 otherwise. Description: A I0I0 I7I

Logic Diagram En I1I1 I3I3 I5I5 I7I7 y0y0 I2I2 I3I3 I6I6 I7I7 y1y1

I0I0 I1I1 I6I6 I7I7 y2y2 I0I0 I1I1 I6I6 I7I7 A..

Priority Encoder Input (I 2 n -1,…, I 0 ) Output (y n-1,…,, y 0 ) (y n-1,…,, y 0 ) = i if I i = 1 & En = 1 & I k = 0 k > i. V Eo = 1 if En = 1 & I i = 0 i, Gs = 1 if En = 1 & i s.t. I i = 1. V E (Gs is like A, and Eo tells us if enable is true or not) En EoGs I0I0 I7I7 y0y0 y1y1 y2y

Implement a 32-input priority encoder w/ 8 input priority encoders (high bit priority). y 32, y 31, y 30 I Eo Gs y 22, y 21, y 20 I Eo Gs y 12, y 11, y 10 I 15-8 Eo Gs y 02, y 01, y 00 I 7-0 Eo Gs En