CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina

Chapter 5: Designing Combinational Systems

10/13/20093 Iterative System A system implemented with multiple copies of a smaller circuit Consider 4-bit adder as an example

10/13/20094 Delay in Combinational Logic Circuits When the input to a gate changes, the output of that gate will not change instantaneously Instead, there is a small delay ∆ If the output of one gate is used as the input to another gate, the delays will add The output is stable after the longest delay path

10/13/20095 Delay in Combinational Logic Circuits Hazard (or glitch)

10/13/20096 Example of Delay

10/13/20097 Cascading 4-bit Adders Can cascade multiple 4-bit adders if larger adders are needed

10/13/20098 Subtractors and Add/Subtractors To do subtraction, we can develop a 1-bit full subtractor and cascade as many of them as necessary On the other hand, we can build an add/subtractor based on an adder because a – b = a + (-b) Will need a signal line which is 0 for addition and 1 for subtraction (called a’/s, i.e. add’/subtract) This is because 1  x = x’ and 0  x = x

10/13/20099 Subtractors and Add/Subtractors

10/13/ Binary Decoder A binary decoder is a device that, when activated, selects one of several output lines, based on a coded input signal The input is an n-bit binary number, and there are 2 n output lines Some decoders also have one or more enable inputs Often used to select one of many devices

10/13/ Active High Decoder

10/13/ Active Low Decoder

10/13/ Decoder with Enable

10/13/ Decoder

10/13/ Decoder

10/13/ Use Decoder to Enable Another Decoder

10/13/ Multiplexers A multiplexer is a switch that passes one of its data inputs through to the output, as a function of a set of select inputs Sets of multiplexers are often used to choose among several multibit input numbers

10/13/ Two-way Multiplexer out = w if S = 0; out = x if S = 1

10/13/ Four-way Multiplexer

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10/13/ Three-variable Function Implemented with Multiplexer

10/13/ Demultiplexer Inverse of a mux: routes a signal from one place to one of many places

10/13/ Three-State Gates Has an enable input If the enable input is active, the gate behaves as usual If the enable input is inactive, the output behaves as if it is not connected

10/13/ A Multiplexer using Three- State Gates if EN = 0, f = a if EN = 1, f = b

10/13/ Gate Arrays Also known as programmable logic device (PLD) or field programmable gate array (FPGA) An efficient way of implementing complicated systems Can implement SOP expressions which are sums of some common product terms

10/13/ Structure of a Gate Array

10/13/ An Example of Gate Array f = a’b’ + abc g = a’b’c’ + ab + bc h = a’b’ + c

10/13/ Three Types of Combinational Logic Arrays Programmable Logic Array (PLA) User specifies all of the connections in both the AND array and the OR array Read-Only Memory (ROM) The AND array is fixed – like a decoder consisting of 2 n AND gates for n inputs User specifies the connections in the OR array Programmable Array Logic (PAL) The connections to the OR gates are specified; user determines the AND gate inputs

10/13/ Only need a list of minterms for each function. For example, W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) Design with Read-Only Memories

10/13/ Structure of a PAL