Introduction to VHDL Multiplexers

Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE standard specification language (IEEE ) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level

Combinational Circuit Example n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel sel y 0 a 1 b

library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; An n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX

library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs generic statement defines width of bus

library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0);

Standard Logic type std_ulogic is (‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care library IEEE; use IEEE.std_logic_1164.all;

Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX Note: <= is signal assignment

architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture entity name process sensitivity list Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

Digilab2 – DIO1 Boards Spartan II FPGA 8 LEDs LD(1:8) 8 Switches SW(1:8) 4 Pushbuttons BTN(1:4) Four 7-segment displays Pushbutton bn 74HC373 latch ldg <= ‘1’

Top-level Design – Lab 1

library IEEE; use IEEE.std_logic_1164.all; entity lab1 is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN4: in STD_LOGIC; ldg: out STD_LOGIC; LD: out STD_LOGIC_VECTOR (1 to 4) ); end lab1;

architecture lab1_arch of lab1 is component mux2g generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end component; constant bus_width: positive := 4; begin ldg <= '1'; -- enable 74HC373 latch SWmux: mux2g generic map(width => bus_width) port map (a => SW(1 to 4), b => SW(5 to 8), sel => BTN4, y => LD); end lab1_arch;

An n-line 4 x 1 multiplexer a(n-1:0) b(n-1 :0) y(n-1 :0) sel(1:0) n-line 4 x 1 MUX c(n-1 :0) d(n-1 :0) Sely “00”a “01”b “10”c “11”d

An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4g is generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mux4g;

Example of case statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4g_arch; Must include ALL posibilities in case statement Note implies operator => Sely “00”a “01”b “10”c “11”d

VHDL Architecture Structure architecture name_arch of name is begin end name_arch; Signal assignments Concurrent statements Process 1 Process 2 Concurrent statements Processes contain sequential statements, but execute concurrently within the architecture body

VHDL Process P1: process (<sensitivity list) begin end process P1; Optional process label Within a process: Variables are assigned using := and are updated immediately. Signals are assigned using <= and are updated at the end of the process.