EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Presentation transcript:

EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design The MOS Transistor

EE415 VLSI Design MOS transistors Symbols D S G D S G G S DD S G NMOS Enhancement NMOS PMOS Depletion Enhancement B NMOS with Bulk Contact Channel

EE415 VLSI Design MOSFET Static Behavior Depletion Region V GS =0 Mobile electrons With drain and source grounded, and V GS = 0, both back-to-back (sub- source, sub-drain) junctions have 0V bias and are OFF

EE415 VLSI Design MOSFET Static Behavior Positive voltage applied to the gate (V GS > 0) The gate and substrate form the plates of a capacitor. Negative charges accumulate on the substrate side (repels mobile holes) A depletion region is formed under the gate (like pn junction diode)

EE415 VLSI Design Inversion As the V GS increases, the surface under the gate undergoes inversion to n- type material. This is the beginning of a phenomenon called strong inversion. Further increases in V GS do not change the width of the depletion layer, but result in more electrons in the thin inversion layer, producing a continuous channel from source to drain

EE415 VLSI Design The Threshold Voltage The value of V GS where strong inversion occurs is called the Threshold Voltage, V T, and has several components: The flat-band voltage, V FB, is the built-in voltage offset across the MOS structure and depends on fixed charge and implanted impurities charge on the oxide-silicon interface V B represents the voltage drop across the depletion layer at inversion and equals to minus twice the Fermi potential ~(0.6V) V ox represents the potential drop across the gate oxide

EE415 VLSI Design The Threshold Voltage Where:  F is the Fermi potential ( ~ -0.3V for p- type substrates Cox is the gate oxide capacitance V SB is the substrate bias voltage V T0 is V T at V SB = 0 Note: V T is positive for NMOS transistors and negative for PMOS

EE415 VLSI Design The Body Effect

EE415 VLSI Design Current-Voltage Relations Assume V GS > V T A voltage difference V DS will cause I D to flow from drain to source At a point x along the channel, the voltage is V(x), and the gate-to- channel voltage is V GS - V(x) For channel to be present from drain to source, V GS - V(x) > V T, i.e. V GS - V DS > V T for channel to exist from drain to source

EE415 VLSI Design Linear (triode) Region When V GS - V DS > V T, the channel exists from drain to source Transistor behaves like voltage controlled resistor

EE415 VLSI Design Saturation Region When V GS - V DS  V T, the channel is pinched off Electrons are injected into depletion region and accelerated towards drain by electric field Transistor behaves like voltage-controlled current source Pinch-off

EE415 VLSI Design Current-Voltage Relations Long-Channel Device

EE415 VLSI Design Current-Voltage Relations Long Channel transistor NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V Quadratic Relationship x V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T cut-off

EE415 VLSI Design A model for manual analysis